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EP-4460877-B1 - METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

EP4460877B1EP 4460877 B1EP4460877 B1EP 4460877B1EP-4460877-B1

Inventors

  • ULKUNIEMI, Riina
  • VILOKKINEN, VILLE
  • MELANEN, PETRI

Dates

Publication Date
20260513
Application Date
20221208

Claims (13)

  1. A method (100) for fabricating a semiconductor device on a semiconductor substrate (202), wherein the semiconductor device is adapted to provide target lasing properties, the method comprising: - creating (102) a mask layer (204) over the semiconductor substrate (202), the mask layer (204) having at least one opening (206) to expose a region of the semiconductor substrate (202); - etching (104) using a first etching process the exposed region (208), utilizing inductively coupled plasma with preselected first set of parameters to obtain a baseline mesa profile (210), the baseline mesa profile having a baseline mesa angle; - re-etching (106) using a second etching process the etched region, utilizing inductively coupled plasma with preselected second set of parameters, to alter the baseline mesa profile (210), the second set of parameters being different from the first preselected parameters, to obtain a requisite mesa profile (220) having a requisite mesa angle defined by the target lasing properties and the requisite mesa angle being different from the baseline mesa angle; - removing (108) the mask layer (204); and - defining (110) a p-n junction (226) for the semiconductor substrate (202).
  2. A method (100) according to claim 1, wherein the preselected first set of parameters are selected based, at least in part, to obtain the baseline mesa profile (210) having a predefined depth.
  3. A method (100) according to claim 2, wherein the second etching process is performed to alter a sidewall profile of the baseline mesa profile (210) to define the requisite mesa angle for the requisite mesa profile (220) while, substantially, retaining same depth for the requisite mesa profile as the predefined depth of the baseline mesa profile.
  4. A method (100) according to any one of claims 1-3, wherein the preselected first set of parameters comprises utilizing the inductively coupled plasma for the first etching process which is denser compared to the inductively coupled plasma utilized as part of the preselected second set of parameters for the second etching process.
  5. A method (100) according to any one of preceding claims, wherein the preselected second set of parameters comprises a preselected etch time for the second etching process, a preselected reactive-ion etching (RIE) power for the inductively coupled plasma and are selected based on the requisite mesa angle.
  6. A method (100) according to any one of preceding claims, wherein the second etching process is an anisotropic etching process.
  7. A method (100) according to any one of preceding claims, wherein defining the p-n junction (226) for the semiconductor substrate (202) further comprises: - depositing an insulating layer (228) over the semiconductor substrate (202); - defining an opening (230) in the insulating layer (228) corresponding to a top area (218) of the requisite mesa profile (220) utilizing photolithography techniques; - forming a p-contact (232) at the top area (218) of the requisite mesa profile (220); and - forming a n-contact (236) on a backside (238) of the semiconductor substrate (202).
  8. A method (100) according to claim 7, wherein the step of forming the n-contact (236) further comprises heating the semiconductor substrate (202) by rapid thermal annealing.
  9. A method (100) according to any one of claims 7 or 8, wherein prior to the step of forming the n-contact (236), the method comprises thinning the semiconductor substrate (202).
  10. A method (100) according to claim 9, wherein the semiconductor substrate (202) is thinned to about 200 micrometres.
  11. A method (100) according to any one of claims 7-10 further comprising: - cleaving the semiconductor substrate (202) to define bars; and - coating facets of the defined bars to form mirrors.
  12. A method (100) according to claim 11 further comprising: - scribing chips off the formed mirrors; and - mounting the scribed chips to form the semiconductor device.
  13. A method (100) according to any one of preceding claims, wherein the mask layer (204) is one of a photoresist mask layer or a hard mask layer.

Description

TECHNICAL FIELD The present disclosure relates to fabrication of semiconductor devices; and more specifically to a method for fabricating a semiconductor device on a semiconductor substrate. BACKGROUND Fabrication methods that are employed to tailor surface properties of semiconductors have become increasingly important as new applications for semiconductor-based materials continue to be developed. Typically, a semiconductor device such as a semiconductor laser is fabricated from semiconductor wafers or substrates, wherein a designated structure is formed via one or more epitaxial methods such as, for example, a metal organic chemical vapor deposition (MOCVD) method. Generally, the formed structure comprises a pin-junction with active region on top of a substrate wafer. Upon proper fabrication of the semiconductor substrate to laser chips, a current is driven through the pn-junction for lasing or laser formation. If only current determines where gain is obtained, device is called a gain-guided laser. It is also possible to enhance gain properties by index-guiding, where optical field is confined with refractive index difference is generated near the active region. This can be implemented by etching a ridge/mesa structure to the semiconductor after epitaxial growth (for example, in Ridge Waveguide (RWG) laser), or it can be done as a part of the epitaxial growth, in which case the ridge is surrounded by other semiconductor material. For best operating properties, sides of the ridge have to be covered with insulating material to ensure proper gain-guiding with current, i.e., only top of the ridge has to be uninsulated. This is usually done by depositing the insulating layer on the whole wafer, then doing photolithographic steps for etching the top of the ridge open. This, in turn, is achieved by leaving stripe with width of the ridge or less exposed to etching, and everything else being covered by photoresist, protecting the region where insulation is needed. After this step, metal is deposited on top of the ridges. Since only the top of the ridge is opened, when the current is driven to the device, the current goes through the semiconductor structure only through the ridge. In the fabrication of mesa-type and similar semiconductor devices, one of the main problems is that of making an electrical contact to the mesa or other protuberance, which is usually very small and protrudes only a few micrometres above the relatively larger area of a surface of the remainder of the semiconductor body. For instance, when fabricating single-mode RWG lasers, ridge width has to be narrow (~1-3 µm, depending on operating wavelength) to ensure the single-mode operation. Due to the narrow widths of the ridge, alignment tolerances are really low. Further, existing semiconductor fabrication techniques are not self-aligning and alignment lithography is required to ease the strict alignments or prevent misalignment of the open mask for further preventing non-symmetric opening of the ridge in which the insulating material covers the ridge partly from one side and exposes ridge side too much from the other side causing current leakage, electrical losses and distortion in the optical field output. Furthermore, insulating material residuals on top of the ridge may cause mechanical issues in cleaving due to the height difference on top of the ridge and also cause non-continuity to of the contact surface on top and reducing the efficiency of operation or yield losses in laser diode processes. Moreover, in silicon photonics, that offers a platform to build mass-producible optical circuits, such that the interest to develop suitable coupling strategies is increased. One of the most important aspects of silicon photonics is the ability to provide extremely small optical components having dimensions of the order of a magnitude smaller than optical fibre devices. Such a dimension difference makes the design of fiber-to-chip interfaces challenging and, over the years, has stimulated considerable technical and research efforts in the field. Therefore, in light of the foregoing discussion, there exists a need to overcome the aforementioned drawbacks associated with existing fabrication techniques and provide an improved method for fabricating semiconductor devices. SUMMARY The present disclosure seeks to provide a method for fabricating a semiconductor device on a semiconductor substrate, wherein the semiconductor device is adapted to provide target lasing properties. An aim of the present disclosure is to provide a solution that overcomes at least partially the problems encountered in prior art. In one aspect, an embodiment of the present disclosure provides a fabricating a semiconductor device on a semiconductor substrate, wherein the semiconductor device is adapted to provide target lasing properties, the method comprising: creating, a mask layer over the semiconductor substrate, the mask layer having at least one opening to expose a region