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EP-4462265-B1 - OPERATIONS IN A PROCESSOR CACHE BASED ON OCCUPANCY STATE

EP4462265B1EP 4462265 B1EP4462265 B1EP 4462265B1EP-4462265-B1

Inventors

  • DUTTA, PRANJAL KUMAR

Dates

Publication Date
20260513
Application Date
20240502

Claims (15)

  1. An apparatus (100), comprising: a cache (800) including a set having a plurality of ways, wherein the cache (800) is configured to: maintain, for the set, occupancy state information (810) indicative of an occupancy of the set, wherein the occupancy state information includes information indicative as to whether the set is full and information indicative as to whether the set is empty, wherein the information indicative as to whether the set is full includes a full-bit which is set in a manner indicative as to whether or not the set is full and wherein the information indicative as to whether the set is empty includes an empty-bit which is set in a manner indicative as to whether or not the set is empty; access, based on a memory operation for the set, at least a portion of the occupancy state information; and perform, based on the at least a portion of the occupancy state information (810), the memory operation.
  2. The apparatus (100) according to claim 1, wherein the occupancy state information (810) includes at least one of a value indicative of a quantity of the ways of the set that are full, or a value indicative of a quantity of ways of the set that are empty.
  3. The apparatus (100) according to any of claims 1 to 2, wherein the occupancy state information (810) includes at least two of a value indicative of a quantity of the ways of the set that are full and a value indicative of a quantity of ways of the set that are empty.
  4. The apparatus (100) according to any of claims 1 to 3, wherein the memory operation is a write operation, wherein the cache (800) is configured to initiate an eviction procedure for the set, without scanning the plurality of ways of the set to look for an empty cache line in which to store a memory block, based on a determination that the at least a portion of the occupancy state information (810) is indicative that the set is full.
  5. The apparatus (100) according to any of claims 1 to 3, wherein the memory operation is a read operation, wherein the cache (800) is configured to select a next set of the cache (800) to search for a memory block, without scanning the plurality of ways of the set to look for the memory block, based on a determination that the at least a portion of the occupancy state information (810) is indicative that the set is empty.
  6. The apparatus (100) according to any of claims 1 to 5, wherein the cache (810) includes a data array (1510), a tag array (1520), and an occupancy state information array (1530), wherein the occupancy state information (810) is maintained within the occupancy state information array (1530).
  7. The apparatus (100) according to any of claims 1 to 6, wherein the occupancy state information (810) includes a bit indicative of an occupancy of the set, wherein the bit indicative of the occupancy of the set is determined based on a respective plurality of occupancy status bits for the ways of the set.
  8. The apparatus (100) according to claim 7, wherein the occupancy status bits are stored in a respective plurality of entries of a tag array (1520) of the cache (1500), wherein the occupancy status bits are indicative as to whether the respective ways are empty or indicative as to whether the respective ways are full.
  9. The apparatus (100) according to any of claims 1 to 8, wherein the memory operation is a write operation for a memory block.
  10. The apparatus (100) according to claim 9, wherein, to perform the write operation for the memory block, the cache (800) is configured to: determine, based on a memory block address of the memory block, that the set is a default set for the memory block; determine, based on the at least a portion of the occupancy state information (810), whether the set is full; and perform the write operation for the memory block based on whether the set is full.
  11. The apparatus (100) according to claim 9, wherein, to perform the write operation for the memory block, the cache (810) is configured to: determine, based on the at least a portion of the occupancy state information (810), that the set is not full; select, from the set, a cache line of the set that is empty; and store the memory block in the cache line of the set that is empty.
  12. The apparatus (100) according to claim 9, wherein, to perform the write operation for the memory block, the cache (800) is configured to: determine, based on the at least a portion of the occupancy state information (810), that the set is full; evict, from the set, a cache line of the set; and store the memory block in the cache line of the set.
  13. The apparatus (100) according to any of claims 1 to 8, wherein the memory operation is a read operation for a memory block.
  14. The apparatus (100) according to claim 13, wherein, to perform the read operation for the memory block, the cache (800) is configured to: determine, based on a memory block address of the memory block, that the set is a default set for the memory block; determine, based on the at least a portion of the occupancy state information (810), whether the set is empty; and perform the read operation for the memory block based on whether the set is empty.
  15. A method, comprising: maintaining, for a cache (800) including a set having a plurality of ways, occupancy state information (810) indicative of an occupancy of the set, wherein the occupancy state information includes information indicative as to whether the set is full and information indicative as to whether the set is empty, wherein the information indicative as to whether the set is full includes a full-bit which is set in a manner indicative as to whether or not the set is full and wherein the information indicative as to whether the set is empty includes an empty-bit which is set in a manner indicative as to whether or not the set is empty; accessing, based on a memory operation for the set, at least a portion of the occupancy state information; and performing, based on the at least a portion of occupancy state information (810), the memory operation.

Description

TECHNICAL FIELD Various example embodiments relate generally to computer systems and, more particularly but not exclusively, to caches associated with processors of computer systems. BACKGROUND Computer systems utilize various types of processors to perform various functions in various contexts. Processors utilize various types of caches to perform various functions in various contexts. CN 111 338 987 A discloses a method for quickly invalidating set associative translation look aside buffer entries, by providing a group valid bit of group corresponding to translation look aside buffer item and row valid bit of corresponding translation look aside buffer item. US 2014/281248 A1 discloses a method obtaining a maximum value indicating maximum number of ways containing modified data in multiple ways and associative data cache and applying a read/write policy recognizing said maximum value. SUMMARY The invention is defined in the appended claims. The dependent claims set out particular embodiments. BRIEF DESCRIPTION OF THE DRAWINGS The teachings herein can be readily understood by considering the following detailed description in conjunction with the accompanying drawings, in which: FIG. 1 depicts an example embodiment of a computing system including a processor and a memory for illustrating an instruction pipeline supported by the processor;FIG. 2 depicts an example embodiment of a processor for use as the processor of the computing system of FIG. 1;FIG. 3 depicts an example embodiment of a multi-core processor including multiple cores and multiple levels of caches;FIG. 4 depicts an example embodiment of an N-way set associative cache for use in a processor;FIG. 5 depicts an example embodiment of a field partitioning an address of a memory block in memory;FIG. 6 depicts an example embodiment of P-tag, P-index, and P-offset mappings of an address of a memory block to be stored in a cache based on a write operation;FIG. 7 depicts an example embodiment of a set associative cache before storing a memory block where occupancy state information is not supported;FIG. 8 depicts an example embodiment of a set associative cache before storing a memory block where occupancy state information is supported;FIG. 9 depicts an example embodiment of a logic circuit configured to determine a full-bit to be used as occupancy state information for a write operation;FIG. 10 depicts an example embodiment of P-tag, P-index, and P-offset mappings of an address of a memory block to be read from a cache based on a read operation;FIG. 11 depicts an example embodiment of a set associative cache before reading a memory block where occupancy state information is not supported;FIG. 12 depicts an example embodiment of a set associative cache before reading a memory block where occupancy state information is supported;FIG. 13 depicts an example embodiment of a logic circuit configured to determine an empty-bit to be used as occupancy state information for a read operation;FIG. 14 depicts an example embodiment of a set associative cache including occupancy state information;FIG. 15 depicts an example embodiment of an N-way set associative cache configured to support use of occupancy state information;FIG. 16 depicts an example embodiment of method for storing a memory block into a set associative cache supporting occupancy state information;FIG. 17 depicts an example embodiment of a method for finding an empty cache line in a set associative cache, for use in conjunction with the method of FIG. 16;FIG. 18 depicts an example embodiment of method for reading a memory block from a set associative cache supporting occupancy state information;FIG. 19 depicts an example embodiment of a method for finding an empty cache line in a set associative cache, for use in conjunction with the method of FIG. 18;FIG. 20 depicts an example embodiment of a method for operating a cache using occupancy state information; andFIG. 21 depicts an example embodiment of a computer suitable for use in performing various functions presented herein. To facilitate understanding, identical reference numerals have been used herein, wherever possible, in order to designate identical elements that are common among the various figures. DETAILED DESCRIPTION Various example embodiments for supporting operation of a processor cache are presented herein. Various example embodiments for supporting operation of a processor cache may be configured to support operation of an N-way set associative cache based on occupancy state information. Various example embodiments for supporting operation of an N-way set associative cache may be configured to support operation of the N-way set associative cache based on occupancy state information where the occupancy state information may be used to support more efficient memory operations on the N-way set associative cache. Various example embodiments for supporting operation of an N-way set associative cache based on occupancy state information may