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EP-4478668-B1 - CIRCUIT, METHOD AND DEVICE FOR ADDRESSING CAN NODES

EP4478668B1EP 4478668 B1EP4478668 B1EP 4478668B1EP-4478668-B1

Inventors

  • PENG, Changyin
  • YANG, JIE
  • WANG, LIN
  • CHEN, FEI

Dates

Publication Date
20260506
Application Date
20231117

Claims (9)

  1. A circuit for addressing CAN nodes, comprising a fuse adapter board, a first cell monitor unit, CMU and a second CMU; wherein the fuse adapter board comprises a short-circuited circuit; the first CMU comprises a first micro-controller unit, MCU and a first CAN identification circuit, wherein a first terminal of the first MCU is connected to a CAN interface in the fuse adapter board through a CAN interface, a second terminal of the first MCU is connected to the first CAN identification circuit, and the second terminal of the first MCU is a GPIO pin of the first MCU; the second CMU comprises a second MCU and a second CAN identification circuit, wherein a first terminal of the second MCU is connected to a CAN interface in the fuse adapter board through the CAN interface, a second terminal of the second MCU is connected to the second CAN identification circuit, and the second terminal of the second MCU is a GPIO pin of the second MCU; the fuse adapter board is connected to the first MCU or the second MCU through the short-circuited circuit, and is configured to control the short-circuited circuit to be shorted to enable a level on a GPIO pin of the first MCU or a GPIO pin of the second MCU connected to the short-circuited circuit to be a low level; the first MCU is configured to set a CAN addressing based on a level on the GPIO pin of the first MCU; and the second MCU is configured to set a CAN addressing based on a level on the GPIO pin of the second MCU.
  2. The circuit according to claim 1, wherein in a case that the fuse adapter board is connected to the first MCU through the short-circuited circuit, and the first CAN identification circuit comprises a first resistor (Rp1); wherein the second terminal of the first MCU is connected to a first terminal of the first resistor (Rp1), the first terminal of the first resistor (Rp1) is grounded through the short-circuited circuit, and a second terminal of the first resistor (Rp1) is connected to a power supply.
  3. The circuit according to claim 2, wherein the second CAN identification circuit comprises a second resistor (Rp2); and the second terminal of the second MCU is connected to a first terminal of the second resistor (Rp2), and a second terminal of the second resistor (Rp2) is connected to the power supply.
  4. The circuit according to claim 1, wherein in a case that the fuse adapter board is connected to the second MCU through the short-circuited circuit, and the second CAN identification circuit comprises a second resistor (Rp2); wherein the second terminal of the second MCU is connected to a first terminal of the second resistor (Rp2), the first terminal of the second resistor (Rp2) is grounded through the short-circuited circuit, and a second terminal of the second resistor (Rp2) is connected to a power supply.
  5. The circuit according to claim 4, wherein the first CAN identification circuit comprises a first resistor (Rp1); and the second terminal of the first MCU is connected to a first terminal of the first resistor (Rp1), and a second terminal of the first resistor (Rp1) is connected to the power supply.
  6. The circuit according to claim 1, wherein the short-circuited circuit comprises a switch; a first terminal of the fuse adapter board is connected to a first terminal of the switch, and a second terminal of the fuse adapter board is connected to a second terminal of the switch; the first terminal of the switch is connected to the second terminal of the first MCU or the second terminal of the second MCU, and the second terminal of the switch is grounded; and the switch is switched on after the first MCU and the second MCU are powered on, to enable the level on the GPIO pin of the first MCU or the GPIO pin of the second MCU connected to the first terminal of the switch to be the low level.
  7. The circuit according to claim 1, wherein, a first terminal of the fuse adapter board is connected to a second terminal of the fuse adapter board; the first terminal of the fuse adapter board is connected to the second terminal of the first MCU or the second terminal of the second MCU, and the second terminal of the fuse adapter board is grounded; wherein the first terminal of the fuse adapter board serves as a first terminal of the short-circuited circuit, and the second terminal of the fuse adapter board serves as a second terminal of the short-circuited circuit; and the first terminal of the fuse adapter board and the second terminal of the fuse adapter board are shorted after the first MCU and the second MCU are powered on, to enable the level on the GPIO pin of the first MCU or the GPIO pin of the second MCU connected to the first terminal of the fuse adapter board to be the low level.
  8. A method for addressing CAN nodes, applied to the circuit for addressing CAN nodes according to any one of claims 1 to 7, wherein the circuit comprises a fuse adapter board, a first CMU and a second CMU, the fuse adapter board comprises a short-circuited circuit, the first CMU comprises a first MCU, and the second CMU comprises a second MCU, and the method comprises: generating a command for CAN peripheral addressing n, on detecting that the first MCU is powered on, the second MCU is powered on, and the short-circuited circuit is shorted; wherein a level on a GPIO pin of the first MCU or a level on a GPIO pin of the second MCU connected to the short-circuited circuit is a low level when the short-circuited circuit is shorted; and sending the command for CAN peripheral addressing n to the first MCU and the second MCU, to enable the first MCU and the second MCU to detect respective levels on respective GPIO pins thereof based on the command for CAN peripheral addressing n; wherein, each of the first MCU and the second MCU sets a respective CAN addressing to the CAN peripheral addressing n on detecting a high level on the respective GPIO pin; and each of the first MCU and the second MCU sets the respective CAN addressing to CAN peripheral addressing n+1 on detecting a low level on the respective GPIO pin.
  9. A device for addressing CAN nodes, applied to the circuit for addressing CAN nodes according to any one of claims 1 to 7, wherein the circuit comprises a fuse adapter board, a first CMU and a second CMU, the fuse adapter board comprises a short-circuited circuit, the first CMU comprises a first MCU, and the second CMU comprises a second MCU, and the device comprises: a CAN peripheral addressing n command generating unit, configured to generate a command for CAN peripheral addressing n, on detecting that the first MCU is powered on, the second MCU is powered on, and the short-circuited circuit is shorted, wherein a level on a GPIO pin of the first MCU or the second MCU connected to the short-circuited circuit is a low level when the short-circuited circuit is shorted; and a CAN peripheral addressing n command sending unit, configured to send the command for CAN peripheral addressing n to the first MCU and the second MCU, to enable the first MCU and the second MCU to detect respective levels of respective GPIO pins thereof based on the command for CAN peripheral addressing n; wherein each of the first MCU and the second MCU sets a respective CAN addressing to the CAN peripheral addressing n on detecting a high level on the respective GPIO pin; and each of the first MCU and the second MCU sets the respective CAN addressing to CAN peripheral addressing n+1 on detecting a low level on the respective GPIO pin.

Description

FIELD The present disclosure relates to the technical field of CAN addressing, and in particular to a circuit, method and device for addressing CAN nodes. BACKGROUND In a conventional energy storage system, two micro-controller units (MCU) are disposed in a cell monitor unit (CMU), in order to be compatible with designs and realize a common platform for circuits. With the two MCUs, the system is compatible with a 0.5C project and a 0.25C project. The 0.25C, 0.5C refer to projects named by a battery charge and discharge rate or capacity. Conventionally, CAN peripherals of the MCUs on the CMU are integrated within the CMU. For the 0.25C project, a pull-down resistor may be added behind each MCU to address the CAN peripherals of the MCUs separately, as shown in Figure 1. In this case, after MCU1 and MCU2 are powered on, a GPIO pin of MCU1 has a high level, and a GPIO pin of MCU2 has a low level. Therefore, for the 0.25C project, the MCU1 and MCU2 can perform independent addressing by identifying levels of GPIO pins, respectively. In contrast, for the 0.5C project, it is required to use two CMU boards. In order to maintain consistency of BOM of the two CMUs, only the MCU1 parts are connected in the two CMUs. As shown in Figure 2, when the two MCU1s are powered on simultaneously, GPIO pins of the two MCU1s both have a high level. In this case, the two MCU1s are unable to address independently by using levels of the GPIO pins of the MCUs. CN 112887443A discloses a domain name resolution query request processing method and device, electronic equipment and a computer readable medium. The method can be used for a domain name resolution server, and comprises the following steps: acquiring a domain name resolution query message, and putting the domain name resolution query message into a query message waiting queue; extracting message information from the domain name resolution query message based on the query message waiting queue, wherein the message information comprises a source IP address, domain name information and a request type; sending the message address of the domain name resolution query message, the domain name information and the request type to a domain name matching waiting queue; sending the source IP address and the message address to a response message query waiting queue; and responding to the domain name resolution query request based on processing results of the domain name matching waiting queue and the message query waiting queue. According to the method, the utilization rate of the central processing unit of the equipment can be improved, the efficiency of the domain name resolution query service is improved, and the response time of the domain name resolution query request is shortened. SUMMARY In view of this, a circuit, method and device for addressing CAN nodes are provided according to the present disclosure, in order to enable two MCU to address independently in the 0.5C project. To this end, technical solutions of the present disclosure are provided as follows. In a first aspect of the present disclosure, a circuit for addressing CAN nodes is provided. The circuit includes a fuse adapter board, a first cell monitor unit, CMU and a second CMU; the fuse adapter board includes a short-circuited circuit; the first CMU includes a first micro-controller unit, MCU and a first CAN identification circuit; where, a first terminal of the first MCU is connected to a CAN interface in the fuse adapter board through a CAN interface; a second terminal of the first MCU is connected to the first CAN identification circuit, and the second terminal of the first MCU is a GPIO pin of the first MCU; the second CMU includes a second MCU and a second CAN identification circuit; where, a first terminal of the second MCU is connected to the CAN interface in the fuse adapter board through a CAN interface; a second terminal of the second MCU is connected to the second CAN identification circuit, and the second terminal of the second MCU is a GPIO pin of the second MCU; the fuse adapter board is connected to the first MCU or the second MCU through the short-circuited circuit, and is configured to control the short-circuited circuit to be shorted to enable a level on a GPIO pin of the first MCU or a GPIO pin of the second MCU connected to the short-circuited circuit to be a low level; the first MCU is configured to set a CAN addressing based on a level on the GPIO pin of the first MCU; and the second MCU is configured to set a CAN addressing based on a level on the GPIO pin of the second MCU. In an embodiment, in a case that the fuse adapter board is connected to the first MCU through the short-circuited circuit, and the first CAN identification circuit includes a first resistor; wherein, the second terminal of the first MCU is connected to a first terminal of the first resistor, the first terminal of the first resistor is grounded through the short-circuited circuit, and a second terminal of the first resistor is c