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EP-4485801-B1 - ADAPTIVE GATE DRIVER WITH NEGATIVE TEMPERATURE COEFFICIENT (NTC) RESISTOR

EP4485801B1EP 4485801 B1EP4485801 B1EP 4485801B1EP-4485801-B1

Inventors

  • RAUT, DILESH ARVIND

Dates

Publication Date
20260513
Application Date
20240618

Claims (11)

  1. A gate drive circuit (400), comprising: at least one semiconductor switch (406, Q4) configured to supply power in response to a control signal received from a control switch (Q1, Q2), the at least one semiconductor switch (406, Q4) associated with: a radiated emissions limit; and a junction temperature; wherein a gate drive voltage of the at least one semiconductor switch (406, Q4) is one of: a positive voltage corresponding to an on state, the on state associated with at least one of a turn-on switching timing or a turn-on switching loss; and a non-positive voltage corresponding to an off state, the off state associated with at least one of a turn-off switching timing or a turn-off switching loss; and a gate resistance device (408) serially connected between the control switch (Q1, Q2) and the at least one semiconductor switch (406, Q4), the gate resistance device thermally coupled to the at least one semiconductor switch (406, Q4), the gate resistance device comprising a negative temperature coefficient "NTC" thermistor (410) and a gate resistor (412) connected in parallel; wherein the NTC thermistor (410) is configured to: sense a junction temperature associated with at least one of the on state or the off state; and in response to a change in the junction temperature, adjust one or more of the associated turn-on or turn-off switching timing or the associated turn-on or turn-off switching loss by adjusting a gate resistance of the gate resistance device, characterised in that the NTC thermistor is configured to reduce the gate resistance based on an inverse linear relationship with an increase in the sensed junction temperature.
  2. The gate drive circuit of any preceding claim, wherein the NTC thermistor is configured to increase the gate resistance based on a reduced current load associated with the gate drive voltage.
  3. The gate drive circuit of any preceding claim, wherein the NTC thermistor is configured to increase the gate resistance based on a reduction in the sensed junction temperature.
  4. The gate drive circuit of any preceding claim, wherein the gate resistor is associated with: a minimum gate resistance corresponding to the radiated emissions limit; and a maximum gate resistance based on a power capacity of the semiconductor switch.
  5. The gate drive circuit of any preceding claim, wherein the at least one semiconductor switch includes at least one insulated gate bipolar transistor "IGBT".
  6. A method for optimal switching of a semiconductor switch, the method comprising: serially connecting a gate resistance device between the semiconductor switch and a control switch of the semiconductor switch, the control switch configured for supplying a gate drive voltage to the semiconductor switch, the semiconductor switch associated with a radiated emissions limit and a junction temperature, the gate drive voltage corresponding to at least one of an on state or an off state, the on state associated with a turn-on switching timing and a turn-on switching loss, the off state associated with a turn-off switching timing and a turn-off switching loss; and the gate resistance device thermally coupled to the semiconductor switch and comprising a negative temperature coefficient "NTC" thermistor and a gate resistor connected in parallel; sensing, via the NTC thermistor, a junction temperature associated with at least one of the on state or the off state; and in response to a change in the junction temperature adjusting one or more of the associated turn-on or turn-off switching timing or the associated turn-on or turn-off switching loss by adjusting , via the NTC thermistor, a gate resistance of the gate resistance device, characterised in that reducing, via the NTC thermistor, a gate resistance of the gate resistance device, includes: reducing the gate resistance based on an inverse linear relationship with an increase in the sensed junction temperature.
  7. The method claim 6, further comprising: increasing, via the NTC thermistor, the gate resistance based on a reduced current load associated with the gate drive voltage, and/or increasing, via the NTC thermistor, the gate resistance based on a reduction in the sensed junction temperature.
  8. The method of any of claims 6 to 7, wherein the gate resistor is associated with: a minimum gate resistance corresponding to the radiated emissions limit; and a maximum gate resistance based on a power capacity of the semiconductor switch.
  9. The method of any of claims 6 to 8, wherein the semiconductor switch is an insulated gate bipolar transistor "IGBT".
  10. The gate drive circuit of any of claims 1 to 5 and the method of any of claims 6 to 9. wherein the at least one semiconductor switch and the gate resistance device includes at least one surface-mounted device "SMD".
  11. The gate drive circuit of any of claims 1 to 5 and the method of any of claims 6 to10, wherein the turn-on switching timing includes at least one of: a turn-on delay associated with the on state; a rise time associated with the on state; or a charging time associated with the on state, and/or, wherein the turn-off switching timing includes at least one of: a turn-off delay associated with the off state; a fall time associated with the off state; or a discharging time associated with the off state.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS The present application claims the benefit under 35 U.S.C. § 119(e) of Indian Provisional Patent Application Serial Number 202311043329 filed June 28, 2023. TECHNICAL FIELD The present disclosure is directed generally to the field of integrated circuitry and particularly to an adaptive gate drive circuit for a semiconductor switching device. BACKGROUND Power inverters for semiconductor devices may convert direct current (DC) into, e.g., three-phase alternating current (AC) and provide the alternating current as a gate drive voltage, switching rapidly between on (e.g., positive voltage) and off (e.g., non-positive voltage, or zero/negative voltage) states controlled by semiconductor switches (e.g., metal oxide semiconductor field effect transistor, MOSFET, or insulated gate bipolar transistor, IGBT). Gate resistors determine how rapidly the semiconductor switches between on and off states. Generally, the faster the switching, the lower the power loss associated with the switching. However, the faster the semiconductor switches switch, the greater the radiation emitted by the semiconductor switches. Comité International Spécial des Perturbations Radioélectriques (CISPR) or equivalent standards provide for maximum allowable radiation levels. Accordingly, gate resistors may be chosen to moderate power losses and enforce radiated emission limits. However, as more current flows through the semiconductor switches, junction temperatures will increase. If gate resistance increases, turn-on switching losses will increase linearly. However, if gate resistance is kept constant, switching delays and switching losses will both increase as junction temperatures rise. US 2020/021102 A1 in its abstract states "The present invention relates to a power converting device, and more particularly, to a power converting device capable of protecting a compressor from overheat, a compressor including the same, and a control method thereof. The device includes an inverter for generating an alternate current for driving the motor using power supplied from a power supply, the inverter including a plurality of switching elements; a driver for driving the plurality of switching elements; a variable resistance unit disposed between and electrically coupled to the driver and a gate of each of the switching elements, wherein the variable resistance unit has a resistance value inversely proportional to a temperature of the inverter; and a controller configured for transferring a drive signal to the driver." CN 107 171 659 A in its abstract states "The invention discloses a semiconductor switch device and an electric power converter. The semiconductor switch device comprises a semiconductor switch, a driving circuit for controlling the turn-on or turn-off of the semiconductor switch, and a variable resistor connected between the output end of the driving circuit and the semiconductor switch, wherein the resistance value of the variable resistor is negatively related to the temperature and capable of measuring the temperature of the semiconductor switch; two same semiconductor switch devices are serially connected in a power supply loop of a controlled circuit as the electric power converter to control the on and off of the controlled circuit; when the temperatures of the semiconductor switches in two semiconductor switch devices are different due to different switch losses, the variable resistor in each of two semiconductor switch devices can adjust the own resistance value according to the characteristic that the resistance value thereof is negatively related to the temperature, the switch loss difference of the semiconductor switches in two semiconductor switch devices is reduced, thereby indirectly reducing the temperature difference of the semiconductor switches in two semiconductor switch devices; the balance of each of the voltage, the switch loss and the temperature between two semiconductor switch devices is realized." (machine translation) DE 10 2010 043109 A1 in its abstract states "The circuit device (2) has a negative temperature coefficient (NTC) resistor (10) that is coupled with a MOSFET (4), through a coupling portion (14). The MOSFET is actuated by pulse width modulation (PWM) signal (8). The NTC resistor is established to influence the rising and falling edges of the PWM signal. An independent claim is included for method for operation of MOSFET using pulse width modulated signal." (machine translation) SUMMARY In a first aspect, an adaptive gate drive circuit according to independent claim 1 is disclosed. In a further aspect, a method for optimal switching of a semiconductor switch according to independent claim 6 is disclosed. Further preferred embodiments are defined in the dependent claims. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not necessarily restrictive of the present di