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EP-4495683-B1 - ARRAY SUBSTRATE AND DISPLAY APPARATUS

EP4495683B1EP 4495683 B1EP4495683 B1EP 4495683B1EP-4495683-B1

Inventors

  • WAN, BIN
  • WANG, XIAOYUAN
  • CHEN, JUNMING
  • YANG, GUODONG
  • PU, Xun
  • ZHU, YUANYUAN
  • FAN, Zhicheng

Dates

Publication Date
20260506
Application Date
20230428

Claims (15)

  1. An array substrate (000) for a display device, having a plurality of sub-pixel regions (00a), the array substrate (000) comprising: a substrate (100); a pixel electrode layer (200) and a common electrode layer (300) that are disposed on the substrate (100); and a plurality of common signal lines (400) disposed on the substrate, wherein the plurality of common signal lines (400) are insulated from the pixel electrode layer (200) and electrically connected to the common electrode layer (300), and an overlapped region is present between an orthographic projection of the common signal lines (400) on the substrate (100) and an orthographic projection of the pixel electrode layer (200) on the substrate (100); wherein the common signal lines (400) have a plurality of electrode structures (400a), wherein different electrode structures (400a) of the plurality of electrodes structures are disposed in different sub-pixel regions, and the plurality of electrode structures (400a) comprise a lap electrode (401) connected to the common electrode layer (300) and an auxiliary electrode (402) not connected to the common electrode layer (300).
  2. The array substrate according to claim 1, wherein an orthographic projection of the auxiliary electrode (402) on the substrate (100) and an orthographic projection of the lap electrode (401) on the substrate (100) have a same shape and a same area.
  3. The array substrate according to claim 1, wherein the plurality of sub-pixel regions (00a) comprise sub-pixel regions (00a) of at least two colors, wherein the plurality of electrode structures (400a) are in one-to-one correspondence with a plurality of the sub-pixel regions (00a) within sub-pixel regions (00a) of a same color, and each of the electrode structures (400a) is disposed in a corresponding one of the sub-pixel regions (00a).
  4. The array substrate according to claim 3, wherein for any adjacent two sub-pixel regions (B1, B2) of the sub-pixel regions (00a) of the same color, one of the two pixel regions (B1) has the lap electrode (401) distributed therein, and the other of the two pixel regions (B2) has the auxiliary electrode (402) distributed therein.
  5. The array substrate according to claim 3, wherein the sub-pixel region in which the electrode structure (400a) is distributed is a blue sub-pixel region (B1, B2).
  6. The array substrate according to claim 1, having a plurality of vias (V1), wherein the common electrode layer (300) is connected to the lap electrode (401) by at least one of the vias (V1), and an orthographic projection of each of the vias (V1) on the substrate (100) is at least partially overlapped with an orthographic projection of the lap electrode (401) on the substrate (100).
  7. The array substrate according to claim 6, wherein one portion of the orthographic projection of the via (V1) on the substrate (100) is within the orthographic projection of the lap electrode (401) on the substrate (100), and the other portion of the orthographic projection of the via (V1) on the substrate (100) is outside the orthographic projection of the lap electrode (401) on the substrate (100).
  8. The array substrate according to any one of claims 1 to 5, wherein the pixel electrode layer (200) is closer to the substrate (100) with respect to the common electrode layer (300), and the pixel electrode layer (200) comprises a pixel electrode (201) disposed within the sub-pixel region (00a), wherein an orthographic projection of the pixel electrode (201) on the substrate (100) is not overlapped with an orthographic projection of the electrode structure (400a) on the substrate (100).
  9. The array substrate according to claim 8, wherein a hollowed-out structure(201a) is formed in the pixel electrode (201), wherein within a same one of the sub-pixel regions (00a), the orthographic projection of the electrode structure (400a) on the substrate (100) is within an orthographic projection of the hollowed-out structure (201a) on the substrate (100).
  10. The array substrate according to claim 9, wherein within the respective sub-pixel regions(OOa), outer boundaries of the orthographic projections of the electrode structures (400a) on the substrate (100) are spaced equally from outer boundaries of the orthographic projections of the hollowed-out structures (201a) on the substrate (100).
  11. The array substrate according to claim 8, further comprising: a plurality of data lines (700), a plurality of gate lines (800), and a plurality of transistors(900), the plurality of transistors (900) being in one-to-one correspondence with a plurality of the pixel electrodes (201); wherein one of the gate lines (800) is electrically connected to a gate electrode(904) of each of the transistors (900) in a same row of the transistors (900), wherein the gate line (800) and the common signal lines (400) are disposed in a same layer and made of a same material, and an extension direction of the gate line (800) is parallel to an extension direction of each of the common signal lines (400); and one of the data lines (700) is electrically connected to a first electrode (901) of each of the transistors (900) in a same column of the transistors (900), and a second electrode (902) of each of the transistors (900) is electrically connected to a corresponding one of the pixel electrodes (201).
  12. The array substrate according to claim 11, wherein for any adjacent two transistors (900) in a column of the transistors (900) that are electrically connected to a same one of the data lines (700), one of the two transistors (900) is disposed on one side of the data line (700), and the other of the two transistors (900) is disposed on the other side of the data line (700).
  13. The array substrate according to claim 11, further comprising: a first insulating layer (500) disposed on a side, away from the substrate (100), of the plurality of transistors (900), and a second insulating layer (600) disposed between the pixel electrode layer (200) and the common electrode layer (300); wherein the pixel electrode layer (200) is disposed on a side, away from the substrate (100), of the first insulating layer (500).
  14. The array substrate according to any one of claims 9 to 13, wherein the common electrode layer (300) has a plurality of slits (301).
  15. A display device, comprising: a color film substrate (001), a liquid crystal layer (002), and the array substrate (000) as defined in any one of claims 1 to 14; wherein the array substrate (000) and the color film substrate (001) are disposed opposite to each other, and the liquid crystal layer (002) is disposed between the array substrate (000) and the color film substrate (001).

Description

TECHNICAL FIELD The present disclosure relates to the field of display technologies, and in particular, relates to an array substrate and a display device. BACKGROUND Nowadays, display devices have become indispensable electronic products in daily life. Display devices such as smart bracelets, mobile phones, and tablet computers have greatly increased the convenience of people's lives. An array substrate for a display device is disclosed in US2020355970 A1. SUMMARY Embodiments of the present disclosure provide an array substrate and a display device. The technical solutions are as follows. According to the claimed subject-matter, an array substrate for a display device is provided. The array substrate has a plurality of sub-pixel regions. The array substrate includes: a substrate;a pixel electrode layer and a common electrode layer that are disposed on the substrate; anda plurality of common signal lines disposed on the substrate, wherein the plurality of common signal lines are insulated from the pixel electrode layer and electrically connected to the common electrode layer, and an overlapped region exits between an orthographic projection of the common signal lines on the substrate and an orthographic projection of the pixel electrode layer on the substrate;wherein the common signal lines have a plurality of electrode structures, wherein different electrode structures of the plurality of electrodes structures are disposed in different sub-pixel regions, and the plurality of electrode structures include a lap electrode connected to the common electrode layer and an auxiliary electrode not connected to the common electrode layer. Optionally, an orthographic projection of the auxiliary electrode on the substrate and an orthographic projection of the lap electrode on the substrate have a same shape and a same area. Optionally, the plurality of sub-pixel regions include sub-pixel regions of at least two colors, wherein the plurality of electrode structures are in one-to-one correspondence with a plurality of the sub-pixel regions within sub-pixel regions of a same color, and each of the electrode structures is disposed in a corresponding one of the sub-pixel regions. Optionally, for any adjacent two sub-pixel regions of the sub-pixel regions of the same color, one of the two pixel regions has the lap electrode distributed therein, and the other of the two pixel regions has the auxiliary electrode distributed therein. Optionally, the sub-pixel region in which the electrode structure is distributed is a blue sub-pixel region. Optionally, the array substrate has a plurality of vias, wherein the common electrode layer is connected to the lap electrode by at least one of the vias, and an orthographic projection of each of the vias on the substrate is at least partially overlapped with an orthographic projection of the lap electrode on the substrate. Optionally, one portion of the orthographic projection of the via on the substrate is within the orthographic projection of the lap electrode on the substrate, and the other portion of the orthographic projection of the via on the substrate is outside the orthographic projection of the lap electrode on the substrate. Optionally, the pixel electrode layer is closer to the substrate with respect to the common electrode layer, and the pixel electrode layer includes a pixel electrode disposed within the sub-pixel region, wherein an orthographic projection of the pixel electrode on the substrate is not overlapped with an orthographic projection of the electrode structure on the substrate. Optionally, a hollowed-out structure is formed in the pixel electrode, wherein within a same one of the sub-pixel regions, the orthographic projection of the electrode structure on the substrate is within an orthographic projection of the hollowed-out structure on the substrate. Optionally, within the respective sub-pixel regions, outer boundaries of the orthographic projections of the electrode structures on the substrate are spaced equally from outer boundaries of the orthographic projections of the hollowed-out structures on the substrate. Optionally, the array substrate further includes: a plurality of data lines, a plurality of gate lines, and a plurality of transistors, the plurality of transistors being in one-to-one correspondence with a plurality of the pixel electrodes; wherein one of the gate lines is electrically connected to a gate electrode of each of the transistors in a same row of the transistors, wherein the gate line and the common signal lines are disposed in a same layer and made of a same material, and an extension direction of the gate line is parallel to an extension direction of each of the common signal lines; andone of the data lines is electrically connected to a first electrode of each of the transistors in a same column of the transistors, and a second electrode of each of the transistors is electrically connected to a corresponding one of the pixel electrodes.