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EP-4498431-B1 - SEMICONDUCTOR PACKAGE STRUCTURE

EP4498431B1EP 4498431 B1EP4498431 B1EP 4498431B1EP-4498431-B1

Inventors

  • FANG, TZU-JUI
  • HUNG, JUI-PIN

Dates

Publication Date
20260513
Application Date
20240702

Claims (10)

  1. A semiconductor package structure (100, 300, 400, 500, 600, 700, 800), comprising: a package substrate (101) comprising: a core structure (102); an integrated capacitor structure (118) embedded in the core structure (102); and a redistribution layer (126) disposed over the integrated capacitor structure (118), the redistribution layer (126) comprising dielectric layers (122) and routing layers (124); and a semiconductor die (130, 132) disposed over the package substrate (101) and electrically coupled to the integrated capacitor structure (118) through the redistribution layer (126); wherein the integrated capacitor structure (118) comprises a first capacitor (114) and a second capacitor (116) which are stacked in a vertical direction relative to a bottom surface (102a) of the core structure (102); wherein the package substrate (101) further comprises an insulating filler (120) disposed in the core structure (102) and surrounding a bottom portion the integrated capacitor structure (118) in the vertical direction; characterized in that a thickness of the insulating filler (120) is less than a thickness of the core structure (102) and less than a thickness of the integrated capacitor structure (118) so as to expose a top portion of the integrated capacitor structure (118); and wherein one of the dielectric layers (122) of the redistribution layer (126) surrounds the exposed top portion of the integrated capacitor structure (118) and is in contact with the insulating filler (120).
  2. The semiconductor package structure (100) as claimed in claim 1, wherein a bottom surface of the integrated capacitor structure (118) is substantially aligned with the bottom surface (102a) of the core structure (102).
  3. The semiconductor package structure (100) as claimed in claim 2, wherein a top surface of the integrated capacitor structure (118) is substantially aligned with a top surface (102b) of the core structure (102).
  4. The semiconductor package structure (100) as claimed in claim 1, wherein the first capacitor (114) and the second capacitor (116) are assembled back-to-back and bonded using an adhesive layer (115), fusion bonding, or hybrid bonding.
  5. The semiconductor package structure (100) as claimed in claim 4, wherein a dimension of the first capacitor (114) is greater than a dimension of the second capacitor (116).
  6. The semiconductor package structure (100, 600, 700) as claimed in claim 1, wherein the second capacitor (116) is disposed over the first capacitor (114) and further comprising a through via electrically coupling the first capacitor (114) to the redistribution layer (126).
  7. The semiconductor package structure (100, 600, 700) as claimed in claim 6, wherein the first capacitor (114) and the second capacitor (116) are bonded using fusion bonding or hybrid bonding.
  8. The semiconductor package structure (100) as claimed in claim 1, wherein the package substrate (101) further comprises: a second redistribution layer (126) disposed below the core structure (102); and a through via extending through the core structure (102) and electrically coupling the redistribution layer (126) to the second redistribution layer (126).
  9. The semiconductor package structure (100) as claimed in claim 1, wherein a top surface (102b) of the integrated capacitor structure (118) is lower than a top surface (102b) of the core structure (102), and the redistribution layer (126) is partially disposed in the core structure (102).
  10. The semiconductor package structure (100) as claimed in claim 1, wherein the semiconductor die (132) vertically overlaps the integrated capacitor structure (118).

Description

BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to semiconductor technology, and, in particular, to a semiconductor package structure that includes a capacitor. Description of the Related Art In addition to providing a semiconductor die with protection from environmental contaminants, a semiconductor package structure can also provide an electrical connection between the semiconductor die packaged inside it and a substrate such as a printed circuit board (PCB). Although existing semiconductor package structures generally meet requirements, they have not been satisfactory in all respects. For example, more and more metal layers in the package substrate are needed to meet demands for high electrical signal performance. However, as the size of semiconductor package structures becomes larger, package substrate warpage becomes a critical issue. Therefore, further improvements in semiconductor package structures are required. Reference may be made to the following documents: US 2022 / 336336 A1 which relates to a semiconductor package and method of fabricating the same;US 2020 / 091063 A1 which relates to a semiconductor structure, package structure, and manufacturing method thereof;US 2022 / 007511 A1 which relates to an electronic component-embedded substrate;US 2009 / 215231 A1 which relates to a method of manufacturing an electronic component built-in substrate;US 2021 / 098323 A1 which relates to an integrated circuit package and method;US 2023 / 062775 A1 which relates to a package substrate, package using the same, and method of manufacturing the same; andUS 2020 / 176417 A1 which relates to a stacked embedded passive substrate structure. BRIEF SUMMARY OF THE INVENTION The present invention is defined by the appended claims. Semiconductor package structures are provided. An exemplary embodiment of a semiconductor package structure includes a package substrate and a semiconductor die. The package substrate includes a core structure, an integrated capacitor structure, and a redistribution layer. The integrated capacitor structure is embedded in the core structure. The redistribution layer is disposed over the integrated capacitor structure. The semiconductor die is disposed over the package substrate and is thermally coupled to the integrated capacitor structure through the redistribution layer. Another embodiment of a semiconductor package structure includes a package substrate. The package substrate includes a core structure, a first capacitor, a second capacitor, a first insulating filler, a first redistribution layer, and a second redistribution layer. The first capacitor and the second capacitor are stacked vertically and are embedded in the core structure. The first insulating filler is disposed in the core structure and surrounds the first capacitor and the second capacitor. The first redistribution layer is disposed below the core structure. The second redistribution layer is disposed over the core structure and is electrically coupled to the first capacitor and the second capacitor. BRIEF DESCRIPTION OF THE DRAWINGS The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: FIGs. 1A to 1E are cross-sectional views of various stages of manufacturing an exemplary semiconductor package structure in accordance with some embodiments of the present disclosure;FIGs. 2A to 2C are cross-sectional views of various stages of manufacturing an exemplary semiconductor package structure in accordance with some embodiments of the present disclosure;FIG. 3 is a cross-sectional view of an exemplary semiconductor package structure in accordance with some embodiments of the present disclosure;FIG. 4 is a cross-sectional view of an exemplary semiconductor package structure in accordance with some embodiments of the present disclosure;FIG. 5 is a cross-sectional view of an exemplary semiconductor package structure in accordance with some embodiments of the present disclosure;FIG. 6 is a cross-sectional view of an exemplary semiconductor package structure in accordance with some embodiments of the present disclosure;FIG. 7 is a cross-sectional view of an exemplary semiconductor package structure in accordance with some embodiments of the present disclosure; andFIG. 8 is a cross-sectional view of an exemplary semiconductor package structure in accordance with some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION The following description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. The present disclosure will be described with respect to particular embodiments and with reference to certain drawings, but the disclosure is not limited thereto and is only limited by the claims. The drawings descr