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EP-4503106-B1 - SEMICONDUCTOR CHIP STRUCTURE

EP4503106B1EP 4503106 B1EP4503106 B1EP 4503106B1EP-4503106-B1

Inventors

  • SEO, JUBIN
  • LIM, DONGCHAN
  • PARK, SUJEONG
  • LEE, JUNKYOUNG

Dates

Publication Date
20260506
Application Date
20240327

Claims (14)

  1. A semiconductor chip structure (1) having a first semiconductor chip (100) including a first chip region (CHR1) and a first scribe lane region (SLR1), the first semiconductor chip being bonded to a second semiconductor chip (200) including a second chip region (CHR2) and a second scribe lane region (SLR2) respectively corresponding to the first chip region and the first scribe lane region, wherein the first semiconductor chip comprises: a first final wiring layer (100c) including a first final wiring pattern (65) and a first passivation layer (64) insulating the first final wiring pattern; and a first bonding wiring layer (100d) disposed on the first final wiring layer, the first bonding wiring layer including a first bonding insulation layer (70) and a first bonding electrode (72) disposed in the first bonding insulation layer, the second semiconductor chip comprises: a second final wiring layer (200d) including at least one second final wiring pattern (22a, 22b), a polish stop pattern (28a, 28b) disposed on the at least one second final wiring pattern, and a second passivation layer (32a, 32b) insulating the at least one second final wiring pattern and the polish stop pattern; and a second bonding wiring layer (200e) disposed on the second final wiring layer, the second bonding wiring layer including a second bonding insulation layer (44) and a second bonding electrode (52) disposed in the second bonding insulation layer and the polish stop pattern, wherein the first bonding insulation layer and the first bonding electrode of the first bonding wiring layer are respectively hybrid-bonded to the second bonding insulation layer and the second bonding electrode of the second bonding wiring layer, and at least a portion of a bonding interface between the hybrid-bonded first bonding insulation layer and the first bonding electrode of the first bonding wiring layer to the second bonding insulation layer and the second bonding electrode of the second bonding wiring layer comprises fine grain copper, and a remaining portion of the bonding interface and an inner portion of each of the first bonding electrode and the second bonding electrode comprise nanotwin copper; characterized in that the fine grain copper is not disposed at an edge of an uppermost surface of the first bonding electrode and an edge of an uppermost surface of the second bonding electrode.
  2. The semiconductor chip structure of claim 1, wherein the fine grain copper has a thickness in a range of about 1 µm to about 1.5 µm with respect to the bonding interface.
  3. The semiconductor chip structure of claim 1 or 2, wherein the fine grain copper has a grain size that is less than or equal to about 300 nm.
  4. The semiconductor chip structure of any preceding claim, wherein: a surface of each of the first final wiring pattern (65) and the first passivation layer (64) is a first planar surface that does not have a step height between the first chip region and the first scribe lane region; and a surface of each of the second final wiring pattern (22a, 22b) and the second passivation layer (32a, 32b) is a second planar surface that does not have a step height between the second chip region and the second scribe lane region.
  5. The semiconductor chip structure of any preceding claim, wherein the first bonding insulation layer (70) and the second bonding insulation layer (44) comprise at least one compound selected from silicon carbide nitride and silicon oxide.
  6. The semiconductor chip structure of any preceding claim, wherein: the first bonding electrode (72) is electrically connected with the first final wiring pattern (65); and the second bonding electrode (52) is electrically connected with at least one of the at least one second final wiring patterns (22a, 22b).
  7. The semiconductor chip structure of any preceding claim, wherein an etch stop layer (66) is disposed on the first final wiring pattern (65) and the first passivation layer (64).
  8. The semiconductor chip structure of any preceding claim, wherein: the first final wiring pattern (65) and the first bonding electrode (72) respectively comprise a different metal material from each other; and the at least one second final wiring pattern (22a, 22b) and the second bonding electrode (52) respectively comprises a different metal material from each other.
  9. The semiconductor chip structure of any preceding claim, wherein a width of the first bonding electrode (72) and a width of the second bonding electrode (52) are different from each other.
  10. The semiconductor chip structure of claim 1, wherein the first semiconductor chip (100) comprises: a first circuit layer (100b) disposed in the first chip region and the first scribe lane region, wherein the first final wiring layer is disposed on the first circuit layer; and wherein the first bonding wiring layer includes a first interlayer insulation layer (68), the first bonding insulation layer being disposed on the first interlayer insulation layer, and the first bonding electrode being disposed in the first interlayer insulation layer and the first bonding insulation layer, wherein the second semiconductor chip comprises: a second circuit layer (200b) disposed in the second chip region and the second scribe lane region, wherein the second final wiring layer is disposed on the second circuit layer; and wherein the second bonding wiring layer includes a second interlayer insulation layer (40), the second bonding insulation layer being disposed on the second interlayer insulation layer, and the second bonding electrode being disposed in the second bonding insulation layer, the second interlayer insulation layer, and the polish stop pattern; wherein the first bonding electrode comprises a first portion having the uppermost surface plated with fine grain copper, and nanotwin copper surrounding a side surface of the first portion and filling the inner portion of the first bonding electrode; and wherein the second bonding electrode comprises a second portion having the uppermost surface plated with fine grain copper, and nanotwin copper surrounding a side surface of the second portion and filling the inner portion of the second bonding electrode.
  11. The semiconductor chip structure of claim 10, wherein at least a portion of the first portion is hybrid-bonded to at least a portion of the second portion.
  12. The semiconductor chip structure of claim 10 or 11, wherein the fine grain copper is formed to have a thickness in a range of about 1 µm to about 1.5 µm with respect to an uppermost surface of the first bonding electrode or the second bonding electrode.
  13. The semiconductor chip structure of any one of claims 10 to 12, wherein the fine grain copper has a grain size that is less than or equal to about 300 nm.
  14. The semiconductor chip structure of any one of claims 10 to 13, wherein the first circuit layer comprises a peripheral circuit (62), and the second circuit layer comprises a memory cell (MC).

Description

1. TECHNICAL FIELD The present inventive concept relates to a semiconductor chip structure, and more particularly, to a semiconductor chip structure including a pad structure. 2. DISCUSSION OF RELATED ART As semiconductor chips are highly integrated, there has been research conducted concerning semiconductor chip structures that are manufactured by bonding a first semiconductor chip to a second semiconductor chip. Semiconductor chip structures manufactured by bonding a first semiconductor chip to a second semiconductor chip should have a high bonding reliability. When the bonding reliability is not good during the manufacturing process, semiconductor chip structures having the first semiconductor chip bonded to the second semiconductor chip may not perform properly. US2022/285208Al discloses a semiconductor chip structure including a first chip that includes a first chip region and a first scribe lane region and a second chip that includes a second chip region and a second scribe lane region respectively bonded to the first chip region and the first scribe lane. CN116487353A discloses structures and methods for direct bonding. SUMMARY Embodiments of the present inventive concept provides a semiconductor chip structure which increases the bonding reliability of a first semiconductor chip and a second semiconductor chip. The invention is defined in claim 1. Preferred embodiments are set out in the dependent claims. The semiconductor chip has a first semiconductor chip including a first chip region and a first scribe lane. The first semiconductor chip is bonded to a second semiconductor chip including a second chip region and a second scribe lane region respectively corresponding to the first chip region and the first scribe lane region. The first semiconductor chip comprises a first final wiring layer including a first final wiring pattern and a first passivation layer insulating the first final wiring pattern. A first bonding wiring layer is disposed on the first final wiring layer. The first bonding wiring layer includes a first bonding insulation layer and a first bonding electrode disposed in the first bonding insulation layer. The second semiconductor chip includes a second final wiring layer including at least one second final wiring pattern, a polish stop pattern disposed on the at least one second final wiring pattern, and a second passivation layer insulating the at least one second final wiring pattern and the polish stop pattern. A second bonding wiring layer is disposed on the second final wiring layer. The second bonding wiring layer includes a second bonding insulation layer and a second bonding electrode disposed in the second bonding insulation layer and the polish stop pattern. The first bonding insulation layer and the first bonding electrode of the first bonding wiring layer are respectively hybrid-bonded to the second bonding insulation layer and the second bonding electrode of the second bonding wiring layer. At least a portion of a bonding interface between the hybrid-bonded first bonding insulation layer and the first bonding electrode of the first bonding wiring layer to the second bonding insulation layer and the second bonding electrode of the second bonding wiring layer comprises fine grain copper, and a remaining portion of the bonding interface and an inner portion of each of the first bonding electrode and the second bonding electrode comprise nanotwin copper, wherein the fine grain copper is not disposed at an edge of an uppermost surface of the first bonding electrode and an edge of an uppermost surface of the second bonding electrode. BRIEF DESCRIPTION OF THE DRAWINGS Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which: FIG. 1 is a cross-sectional view for describing a semiconductor chip structure according to an embodiment;FIG. 2 is a partial cross-sectional view for describing the semiconductor chip structure of FIG. 1;FIGS. 3A to 3C are partial cross-sectional views for describing a semiconductor chip structure according to an embodiment;FIGS. 4 to 13 are cross-sectional views for describing a method of manufacturing a semiconductor chip structure according to an embodiment illustrated in FIGS. 1 and 2;FIG. 14 is a cross-sectional view for describing a semiconductor chip structure according to an embodiment;FIGS. 15 and 16 are cross-sectional views for describing a method of manufacturing the semiconductor chip structure of FIG. 14;FIG. 17 is a block diagram schematically illustrating a memory card to which a semiconductor package including a semiconductor chip structure according to an embodiment is applied; andFIG. 18 is a block diagram schematically illustrating an electronic system to which a semiconductor package including a semiconductor chip structure according to an embodiment is applied. DETAILED DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments will be described in detai