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EP-4513757-B1 - DEVICE FOR MONITORING ONE OR MORE POWER SUPPLIES

EP4513757B1EP 4513757 B1EP4513757 B1EP 4513757B1EP-4513757-B1

Inventors

  • SAMIR, ANASS
  • GIRAUD, BASTIEN
  • RICAVY, Sébastien

Dates

Publication Date
20260513
Application Date
20240808

Claims (11)

  1. Device comprising: - at least one circuit (2000), said at least one circuit (2000) comprising: a first node (2002) configured to receive a reference potential (GND); a second node (2004) configured to receive a first DC voltage (V1), the first DC voltage being a power supply voltage (VDDE, VDD); a third node (2006) configured to receive a second DC voltage (V2); a first NMOS transistor (MN1) having its gate connected to the second node; a second NMOS transistor (MN2) having its drain connected to the source of the first transistor (MN1) and its source connected to the second node; a third NMOS transistor (MN3) having its gate connected to the second node and its source connected to the first node; a fourth PMOS transistor (MP3) having its drain connected to the drain of the third transistor (MN3) and to the gate of the second transistor (MN2) and its gate connected to the source of the first transistor (MN1); a first resistive element (2008) connected between the drain of the first transistor (MN1) and the third node; a second resistive element (2010) connected between the source of the fourth transistor (MP3) and the third node; and a first CMOS inverter (INV3) configured to be powered with the second voltage (V2), an input of the first inverter being connected to the drain of the third transistor (MP3) and an output of the first inverter being configured to deliver a reset signal (POR2000), and - a voltage generation circuit configured to deliver the second DC voltage (V2) at a non-zero value before a powering on and a ramping up of the first voltage (V1), the non-zero value being adapted to allowing a switching to the on state of the fourth transistor (MP3) of said at least one circuit from the powering on of the first voltage (V1).
  2. Device according to claim 1, wherein each of the first and second resistive elements (2008, 2010) is implemented by a PMOS transistor (MP1, MP2) having its gate connected to the first node and its source connected to the third node.
  3. Device according to claim 1 or 2, wherein said at least one circuit (2000) further comprises a capacitive element (Cc) connected between the gate and source of the first transistor (MN1).
  4. Device according to any of claims 1 to 3, wherein said at least one circuit (2000) further comprises a second CMOS inverter (INV4) configured to be powered with the second voltage (V2), an input of the second inverter being connected to the output of the first inverter (INV3), and an output of the second inverter being configured to deliver a signal (nPOR2000) complementary to the reset signal (POR2000).
  5. Device according to any of claims 1 to 4, wherein the first and second resistive elements (2008, 2010), and the first and fourth transistors (MN1, MP3) are sized so that the fourth transistor (MP3) is off when the first transistor is on (MN1).
  6. Device according to any of claims 1 to 5, wherein the second voltage (V2) also is a power supply voltage (VDDE, VDD).
  7. Device according to any of claims 1 to 6, wherein: said at least one circuit (2000) comprises at least two circuits (2000); the device comprises a CMOS logic gate (3002) configured to implement a Boolean AND logic function between the reset signals (POR2000) delivered by said at least two circuits, wherein: the first nodes (2002) of said at least two circuits are configured to receive the same reference potential (GND); the third nodes (2006) of said at least two circuits are configured to receive the second voltage delivered by the voltage generation circuit, said second voltage being a reference voltage (VrefH); and the second nodes (2004) of said at least two circuits are each configured to receive a first DC power supply voltage (VDDE, VDD) different from the first voltages received by the second nodes of the other circuits.
  8. Device according to claim 7, wherein the CMOS logic gate (3002) is configured to be powered with the second voltage (VrefH) delivered by the voltage generation circuit.
  9. Device according to claim 7 or 8, wherein the voltage generation circuit is configured to deliver the second DC reference voltage at its nominal value prior to the powering on and the ramping up of each of the first voltages (VDDE, VDD) .
  10. Device according to claim 7 or 8, wherein the circuit (REFGEN) for generating the second reference voltage (VrefH) comprises: a first voltage dividing bridge (200) connected between a first power supply node (202) configured to receive one of the first DC power supply voltages (VDDE) and a second power supply node (204) configured to receive the reference potential (GND); a first MOS transistor (Ten) and a second resistive voltage dividing bridge (208) connected in series between the first and second power supply nodes (202, 204), the first transistor having its gate connected to an intermediate node (206) of the first bridge and its source connected to the second power supply node (204); a first buffer circuit (BUFFa1) configured to be powered with said one of the first DC power supply voltages (VDDE) and comprising an input (220) connected to a first intermediate node (214) of the second bridge and an output (218) configured to deliver the second reference voltage (VrefH); and a second MOS transistor (To1) having its drain connected to the output of the first buffer circuit and its source connected to the first power supply node (202), wherein the first bridge (200) is configured so that the first transistor (Ten) is off when said one of the first DC power supply voltages (VDDE) is at a value lower than a first threshold, itself lower than a breakdown voltage of the transistors, and wherein the second transistor (To1) is configured to be in the on state if the first transistor (Ten) is off, and conversely.
  11. Device according to claim 7 or 8, wherein the circuit (REFGEN) for generating the second reference voltage (VrefH) comprises: a first voltage dividing bridge (200) connected between a first power supply node (202) configured to receive one of the first DC power supply voltages (VDDE) and a second power supply node (204) configured to receive the reference potential (GND); a first MOS transistor (Ten) and a second resistive voltage dividing bridge (208) connected in series between the first and second power supply nodes (202, 204), the first transistor having its gate connected to an intermediate node (206) of the first bridge and its source connected to the first power supply node (202); a second MOS transistor (T8) and a third resistive voltage dividing bridge (400) connected in series between the first and second power supply nodes (202, 204), the source of the second MOS transistor (T8) being connected to the second power supply node (202, 204); a buffer circuit (BUFFa2) configured to be powered with said one of the first DC power supply voltages (VDDE) and comprising an input (220) connected to a first intermediate node (406) of the third bridge (400) and an output (218) configured to deliver the second reference voltage (VrefH); and a third MOS transistor (To2) having its drain connected to the output of the buffer circuit (BUFFa2) and its source connected to the first power supply node (202); wherein the second transistor (T8) is configured to be in the off, respectively on, state when the first transistor (Ten) is in the off, respectively on, state, wherein the third transistor (To2) is configured to be in the on state if the second transistor (T8) is in the off state, and conversely, and wherein the first bridge (200) is configured so that the first transistor (Ten) is off when said one of the first DC power supply voltages (VDDE) is at a value lower than a first threshold, itself lower than a breakdown voltage of the transistors.

Description

technical field This description relates generally to the monitoring of one or more supply voltages, and, more specifically, to power-on reset (POR) strategies. Previous technique Known chips increasingly include multiple supply voltage domains and/or portions of the chip with circuits using multiple supply voltages. When a supply voltage is off, it is in a high-impedance state. When it is turned on, or energized, this supply voltage initially has a zero value before reaching its nominal or target value following a power-up phase. During the energization and power-up of one or more supply voltages to a portion of the chip, numerous problems arise in the circuits that receive this or these supply voltages for power. An example of a supply voltage detection circuit is described in the patent application. US 2010/0244805 A1 . Known circuits generate, during the power-up of one or more supply voltages, a reset signal that allows the circuits powered by that supply voltage(s) to be brought to a known initial state. Examples of such circuits are described, for example, in the patent application. US 2006/0208777 A1 and in the article "A Sequence Independent Power-on-Reset Circuit for Multi-Voltage Systems" by Khan et al. However, these known power-on reset circuits have many drawbacks. Summary of the invention There is a need for a power-on reset circuit that overcomes all or some of the drawbacks of known power-on reset circuits. For example, there is a need for a power-on reset circuit that consumes less power than known power-on reset circuits. For example, there is a need for a power-up reset device that is independent of the ramp-up sequence of the supply voltages it monitors. For example, there is a need for a power-on reset device that provides a reset signal having a defined state as soon as one of the supply voltages monitored by the device is turned on and is no longer in a high impedance state. For example, there is a need for a power-up reset device that allows implementation with MOS (Metal Oxide Semiconductor) transistors having a Vmax voltage withstand limit, while one of the supply voltages monitored by this device has a higher nominal value than this Vmax voltage withstand and/or the difference in values between two of the voltages monitored by the device can be greater than this Vmax voltage withstand. One embodiment overcomes all or part of the drawbacks of known power-up reset circuits and devices. One embodiment provides for a device comprising at least one circuit, said at least one circuit comprising: a first node configured to receive a reference potential; a second node configured to receive a first DC voltage, the first DC voltage being a supply voltage; a third node configured to receive a second DC voltage; a first NMOS transistor having its gate connected to the second node; a second NMOS transistor having its drain connected to the source of the first transistor and its source connected to the second node; a third NMOS transistor having its gate connected to the second node and its source connected to the first node; a fourth PMOS transistor having its drain connected to the drain of the third transistor and to the gate of the second transistor, and its gate connected to the source of the first transistor; a first resistive element connected between the drain of the first transistor and the third node; a second resistive element connected between the source of the fourth transistor and the third node; and a first CMOS inverter configured to be powered by the second voltage, one input of the first inverter being connected to the drain of the third transistor and one output of the first inverter being configured to provide a reset signal. In one embodiment, each of the first and second resistive elements is implemented by a transistor PMOS with its grid connected to the first node and its source connected to the third node. According to one embodiment, the circuit further includes a capacitive element connected between the gate and the source of the first transistor. According to one embodiment, the circuit further includes a second CMOS inverter configured to be powered by the second voltage, an input of the second inverter being connected to the output of the first inverter, and an output of the second inverter being configured to provide a complementary signal to the reset signal. According to one embodiment, the first and second resistive elements, and the first and fourth transistors are sized so that the fourth transistor is blocked when the first transistor is conducting. According to one embodiment, the second voltage is also a supply voltage. According to the invention, the device comprises: at least one circuit as defined above, and a voltage generation circuit configured to provide the second DC voltage at a non-zero value before the first voltage is powered on and ramped up, the non-zero value being adapted to allow switching to the on state of the fourth transistor as soon