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EP-4517730-B1 - DISPLAY SUBSTRATE AND DISPLAY APPARATUS

EP4517730B1EP 4517730 B1EP4517730 B1EP 4517730B1EP-4517730-B1

Inventors

  • CHEN, Yipeng
  • SHI, LING

Dates

Publication Date
20260506
Application Date
20220525

Claims (15)

  1. A display substrate, comprising: a base substrate, a plurality of sub-pixels (100), located on the base substrate, wherein each of the plurality of sub-pixels (100) comprises a light-emitting element (100b) and a pixel circuit (100a), the pixel circuit (100a) is configured to drive the light-emitting element (100b), the pixel circuit (100a) comprises a plurality of transistors (200) and a storage capacitor (400), each of the plurality of transistors (200) comprises a gate electrode, a first electrode, and a second electrode; a plurality of signal lines (300), arranged on the base substrate, comprising a first initialization signal line (302), a reset control signal line (301), and a second initialization signal line (303) which extend in a first direction (X) and are arranged in a second direction (Y), wherein the reset control signal line (301) is configured to supply a reset control signal to the pixel circuit (100a), the first initialization signal line (302) is configured to supply a first initialization signal to the pixel circuit (100a), and the second initialization signal line (303) is configured to supply a second initialization signal to the pixel circuit (100a), the second direction (Y) intersects with the first direction (X), wherein the plurality of transistors (200) comprise a first reset transistor (T1) and a second reset transistor (T7), a first electrode of the first reset transistor (T1) is electrically connected with the first initialization signal line (302), and a gate electrode of the first reset transistor (T1) and a gate electrode of the second reset transistor (T7) are electrically connected with the reset control signal line (301), a first electrode of the second reset transistor (T7) is electrically connected with the second initialization signal line (303), and a second electrode of the second reset transistor (T7) is electrically connected with the light-emitting element (100b), an orthographic projection of at least one of the first initialization signal line (302) and the second initialization signal line (303) on the base substrate does not overlap with an orthographic projection of the reset control signal line (301) on the base substrate, wherein the plurality of transistors (200) further comprise a refresh control transistor (T8), a first electrode of the refresh control transistor (T8) is electrically connected with a first electrode (401) of the storage capacitor (400), a second electrode of the refresh control transistor (T8) is electrically connected with a second electrode of the first reset transistor (T1), the plurality of signal lines (300) further comprise a refresh gate line (305), the refresh gate line (305) extends in the first direction (X), a gate electrode of the refresh control transistor (T8) is electrically connected with the refresh gate line (305), and the orthographic projection of the second initialization signal line (303) on the base substrate at least partially overlaps with an orthographic projection of the refresh gate line (305) on the base substrate, wherein the plurality of signal lines (300) further comprise a scan control signal line (306), the scan control signal line (306) extends in the first direction (X); the plurality of transistors (200) further comprise a compensation transistor (T2)and a data writing transistor (T4), and the scan control signal line (306) is electrically connected with a gate electrode of the compensation transistor (T2)and a gate electrode of the data writing transistor (T4), respectively, in the second direction (Y), the reset control signal line (301), the refresh gate line (305), and the scan control signal line (306) are arranged sequentially in this order, and the orthographic projection of the second initialization signal line (303) on the base substrate does not overlap with an orthographic projection of the scan control signal line (306) on the base substrate.
  2. The display substrate according to claim 1, wherein the plurality of transistors (200) further comprise a driving transistor (T3), a first light-emitting control transistor (T5), and a second light-emitting control transistor (T6), and the plurality of signal lines (300) further comprise a light-emitting control signal line (304), the light-emitting control signal line (304) extends in the first direction (X), a first electrode of the first light-emitting control transistor (T5) is electrically connected with a second electrode (402) of the storage capacitor (400), a first electrode of the second light-emitting control transistor (T6) is electrically connected with the second electrode of the second reset transistor (T7), and a gate electrode of the first light-emitting control transistor (T5) and a gate electrode of the second light-emitting control transistor (T6) are electrically connected with the light-emitting control signal line (304), and a second electrode of the second light-emitting control transistor (T6) and a second electrode of the first light-emitting control transistor (T5) are connected with a first electrode and a second electrode of the driving transistor (T3), respectively, and a gate electrode of the driving transistor (T3) is connected with a first electrode of the storage capacitor (400), an orthographic projection of the first initialization signal line (302) on the base substrate at least partially overlaps with an orthographic projection of the light-emitting control signal line (304) on the base substrate.
  3. The display substrate according to claim 2, wherein the refresh control transistor (T8) is electrically connected with the compensation transistor (T2), and the refresh control transistor (T8) is configured to be turned on to realize a connection between the gate electrode of the driving transistor (T3) and the compensation transistor (T2) in response to a refresh control signal (Ga3) or is configured to be turned off to realize a disconnection between the gate electrode of the driving transistor (T3) and the compensation transistor (T2).
  4. The display substrate according to any one of claims 1-3, wherein the first initialization signal line (302) and the second initialization signal line (303) are arranged to be spaced apart in the second direction (Y), optionally, wherein the orthographic projection of the reset control signal line (301) on the base substrate does not overlap with an orthographic projection of a signal line of the plurality of signal lines (300) extending in the first direction (X) on the base substrate.
  5. The display substrate according to claim 3, wherein in the second direction (Y), the first initialization signal line (302), the reset control signal line (301), the second initialization signal line (303), the scan control signal line (306), and the storage capacitor (400) are sequentially arranged at intervals, and a minimum spacing between the reset control signal line (301) and the second initialization signal line (303) is greater than a minimum spacing between the refresh gate line (305) and the storage capacitor (400).
  6. The display substrate according to claim 2, wherein the first initialization signal line (302) comprises a first body portion (3021) and at least one first connection portion (3022), the first body portion (3021) extends in the first direction (X), and an orthographic projection of the first body portion (3021) on the base substrate at least partially overlaps with the orthographic projection of the light-emitting control signal line (304) on the base substrate, the at least one first connection portion (3022) is connected with the first body portion (3021), in the second direction (Y), an orthographic projection of the at least one first connection portion (3022) on the base substrate is located between the orthographic projection of the light-emitting control signal line (304) on the base substrate and the orthographic projection of the reset control signal line (301) on the base substrate.
  7. The display substrate according to claim 6, wherein the pixel circuit (100a) comprises an active pattern, the active pattern comprises a channel region (501) and a source and drain region (502) of the transistor (200), and the active pattern comprises a plurality of active portions (503), and each of the plurality of active portions (503) comprises a first end (5031) and a second end (5032) located on both sides of the channel region (501), optionally, wherein the plurality of active portions (503) comprise a first active portion (504), the first active portion (504) extends in the second direction (Y), a first end of the first active portion (504) serves as the first electrode of the first reset transistor (T1), a second end of the first active portion (504) serves as a second electrode of the first reset transistor (T1), and an orthographic projection of first active portion (504) on the base substrate does not overlap with the orthographic projection of the first body portion (3021) of the first initialization signal line (302) on the base substrate, optionally, wherein the plurality of active portions (503) further comprise a second active portion (505), the second active portion (505) extends in the second direction (Y), a first end of the second active portion (505) serves as the first electrode of the first light-emitting control transistor (T5), and an orthographic projection of the second active portion (505) on the base substrate at least partially overlap with the orthographic projection of the first body portion (3021) of the first initialization signal line (302) on the base substrate.
  8. The display substrate according to claim 7, wherein the second initialization signal line (303) comprises a second body portion (3031) and a second connection portion (3032), the second body portion (3031) extends in the first direction (X), one end of the second connection portion (3032) is connected with the second body portion (3031), the second connection portion (3032) of the second initialization signal line (303) is located on a side of the reset control signal line (301) that is closest to the second body portion (3031) of the second initialization signal line (303), optionally, wherein the second body portion (3031) comprises a first bent portion (3033), the reset control signal line (301) comprises a second bent portion (3010), in the second direction (Y), the first bent portion (3033) is bent toward the reset control signal line (301) that is closest thereto, and the second bent portion (3010) is bent toward the light-emitting control signal line (304) that is closest thereto, and a bent direction of the first bent portion (3033) is the same as a bent direction of the second bent portion (3010), optionally, wherein the second connection portion (3032) comprises a first combination portion (30321) and a second combination portion (30322) that are opposite to each other, the plurality of active portions (503) further comprise a third active portion (506), the third active portion (506) extends in the second direction (Y), and a first end (5061) of the third active portion (506) serves as the first electrode of the second reset transistor (T7), a second end (5062) of the third active portion (506) serves as the second electrode of the second reset transistor (T7), the first combination portion (30321) is connected with the first bent portion (3033), and the second combination portion (30322) is electrically connected with the first end (5061) of the third active portion (506).
  9. The display substrate according to any one of claims 1-8, wherein in the second direction (Y), the first initialization signal line (302) is located between the first electrode of the first reset transistor (T1) and the storage capacitor (400), and the orthographic projection of the first initialization signal line (302) on the base substrate does not overlap with an orthographic projection of the storage capacitor (400) on the base substrate.
  10. The display substrate according to claim 3, wherein the pixel circuit (100a) further comprises an active component (5300), the active component (5300) extends in the second direction (Y), the refresh gate line (305) comprises a first refresh gate sub-line (3051) and a second refresh gate sub-line (3052), the first refresh gate sub-line (3051) and the second refresh gate sub-line (3052) both extend in the first direction (X), and in a direction perpendicular to the base substrate, the first refresh gate sub-line (3051), the active component (5300), and the second refresh gate sub-line (3052) are arranged sequentially, and the second refresh gate sub-line (3052) is located on a side of the active component (5300) away from the base substrate; an orthographic projection of the first refresh gate sub-line (3051) on the base substrate at least partially overlaps with an orthographic projection of the active component (5300) on the base substrate to form a first overlap region (3531), an orthographic projection of the second refresh gate sub-line (3052) on the base substrate at least partially overlaps with an orthographic projection of the first overlap region (3531) on the base substrate to form a second overlap region (3532), a portion of the first refresh gate sub-line (3051) and a portion of the second refresh gate sub-line (3052) that are located in the second overlap region (3532) serve as a top gate electrode and a bottom gate electrode of the gate electrode of the refresh control transistor (T8), respectively, and the orthographic projection of the second initialization signal line (303) on the base substrate at least partially overlaps with an orthographic projection of the second overlap region (3532) on the base substrate.
  11. The display substrate according to claim 10, further comprising: a first conductive layer (510), a second conductive layer (520), a third conductive layer (540), a first connection layer (550), and a second connection layer (560), the active pattern is arranged on the base substrate, the first conductive layer (510), the second conductive layer (520), the third conductive layer (540), the first connection layer (550), and the second connection layer (560) are sequentially arranged on a side of the active pattern away from the base substrate in a direction perpendicular to the base substrate, the light-emitting control signal line (304), the reset control signal line (301), the scan control signal line (306), and the first electrode (401) of the storage capacitor (400) are located in the first conductive layer (510); the first refresh gate sub-line (3051) and the second electrode (402) of the storage capacitor (400) are located in the second conductive layer (520); the first initialization signal line (302) and the second refresh gate sub-line (3052) are located in the third conductive layer (540); the second initialization signal line (303) is located in the first connection layer (550); the display substrate further comprises a plurality of data lines (307) and a plurality of power supply signal lines (308), and the plurality of data lines (307) and the plurality of power supply signal lines (308) are in the same layer as the second connection layer (560).
  12. The display substrate according to claim 10, wherein both the first connection layer (550) and the second connection layer (560) comprise a plurality of connection electrodes, the first connection layer (550) comprises a first connection electrode (L1), the second connection layer (560) comprises a second connection electrode (L2), and the first connection electrode (L1) and the second connection electrode (L2) are electrically connected through a first via hole (N1), and the second connection electrode (L2) is electrically connected with the light-emitting element (100b) through a second via hole (N2), the second electrode of the second reset transistor (T7) is connected with the first connection electrode (L1) through a third via hole (N3), and is further electrically connected with the light-emitting element (100b);
  13. The display substrate according to claim 12, wherein an overlap area between the orthographic projection of the first initialization signal line (302) on the base substrate and orthographic projections of the first connection electrode (L1) and the second connection electrode (L2) on the base substrate is less than 5% of an area of an orthographic projection of the first connection electrode (L1) on the base substrate.
  14. The display substrate according to any one of claims 11-13, wherein the first connection layer (550) further comprises a third connection electrode (L3), a fourth connection electrode (L4), a fifth connection electrode (L5), a sixth connection electrode (L6), a seventh connection electrode (L7), and an eighth connection electrode (L8), the second connection layer (560) further comprises a ninth connection electrode (L9), the first initialization signal line (302) is electrically connected with the third connection electrode (L3) through a fourth via hole (N4), the first electrode of the first reset transistor (T1) is electrically connected with the third connection electrode (L3) through a fifth via hole (N5), and the second electrode of the refresh control transistor (T8) is electrically connected with the fourth connection electrode (L4) through a sixth via hole (N6), and the second electrode of the first reset transistor (T1) is electrically connected with the fourth connection electrode (L4) through a seventh via hole (N7); a first electrode of the compensation transistor (T2)is electrically connected with the second electrode of the refresh control transistor (T8) through the sixth via hole (N6), and an orthographic projection of the fourth connection electrode (L4) on the base substrate at least partially overlaps with the orthographic projection of the second initialization signal line (303) on the base substrate; the gate electrode of the driving transistor (T3) is electrically connected with the storage capacitor (400) and the fifth connection electrode (L5) through an eighth via hole (N8), and the first electrode of the refresh control transistor (T8) is electrically connected with the fifth connection electrode (L5) through a ninth via hole (N9); the data writing transistor (T4) is electrically connected with the sixth connection electrode (L6) through a tenth via hole (N10), the sixth connection electrode (L6) is electrically connected with the data line (307) through an eleventh via hole (N11), an orthographic projection of the sixth connection electrode (L6) on the base substrate does not overlap with the orthographic projection of the second initialization signal line (303) on the base substrate; the first light-emitting control transistor (T5) is electrically connected with the seventh connection electrode (L7) through a twelfth via hole (N12), and the seventh connection electrode (L7) is electrically connected with the power supply signal line (308) through a thirteenth via hole (N13), and an orthographic projection of the thirteenth via hole (N13) on the base substrate at least partially overlaps with the orthographic projection of the first initialization signal line (302) on the base substrate; the first electrode of the second light-emitting control transistor (T6) is electrically connected with the eighth connection electrode (L8) through a fourteenth via hole (N14), and the eighth connection electrode (L8) is electrically connected with the ninth connection electrode (L9) through a fifteenth via hole (N15), the ninth connection electrode (L9) is electrically connected with the light-emitting element (100b) through a sixteenth via hole (N16), and orthographic projections of the eighth connection electrode (L8) and the ninth connection electrode (L9) on the base substrate substantially do not overlap with the orthographic projection of the first initialization signal line (302) on the base substrate; optionally, wherein in the second direction (Y), the fourth via hole (N4), the fifth via hole (N5), the twelfth via hole (N12), the fourteenth via hole (N14), and the fifteenth via hole (N15) are located between the light-emitting control signal line (304) and the reset control signal line (301); the sixth via hole (N6), the seventh via hole (N7), the tenth via hole (N10), and the eleventh via hole (N11) are located between the reset control signal line (301) and the second initialization signal line (303); the ninth via hole (N9) is located between the second initialization signal line (303) and the storage capacitor (400), and an orthographic projection of the ninth via hole (N9) on the base substrate at least partially overlaps with an orthographic projection of the scan control signal line (306) on the base substrate.
  15. A display device, comprising the display substrate according to any one of claims 1- 14.

Description

TECHNICAL FIELD The embodiments of the present disclosure relate to a display substrate and a display device. BACKGROUND At present, in a field of display technology, according to a manufacture technology and a material classification of a thin film transistor (TFT), the TFT can include an amorphous silicon (a-Si) TFT, a low temperature polysilicon (LTP) TFT, an oxide (for example, Indium Gallium Zinc Oxide (IGZO)) TFT and the like. The LTPS TFT is manufactured based on a low-temperature polysilicon process, which can achieve smaller drive current and lower drive voltage; the oxide TFT is manufactured based on an oxide process, which can achieve a lower refresh rate. Low temperature polycrystalline oxide (LTPO) is a low power consumption display technology. The LTPO technology integrates the low-temperature polysilicon process and the oxide process, and prepares the LTPS TFT and the oxide TFT in a display panel, which combines advantages of the LTPS TFT and advantages of the oxide TFT, so as to furthest use an advantage of ultra-high mobility rate of the low-temperature polysilicon and an advantage of small leakage current of the oxide to achieve better display performance. US 2021/0134917 A1 discloses a display panel and a display apparatus. The display panel includes a driving array layer having functional layers and insulation layers. The driving array layer includes a first transistor, a second transistor, a first capacitor including a first plate and a second plate, and a second capacitor including a third plate and a fourth plate. An active layer of the first transistor contains silicon, and an active layer of the second transistor contains oxide semiconductor. The first plate and the second plate are located in two of the functional layers, respectively, and the third plate and the fourth plate are located in two of the functional layers, respectively. US 2023/0076760 A1 discloses a display panel and a display device. The display panel includes a pixel circuit, a light-emitting element, and a signal line group. The pixel circuit includes a driving transistor, a data writing transistor, and a first transistor. The first electrode of the first transistor in a first metal layer is connected to a gate of the driving transistor. A side of the first electrode of the first transistor facing the first electrode of the data writing transistor is a first edge and a side of a first electrode of the data writing transistor facing the first electrode of the first transistor is a second edge. Orthographically projected on a plane parallel to the display panel, at least a partial region of at least one signal line is located between the first edge and the second edge, and is arranged in a layer different from the first metal layer. US 2023/0060341A1 discloses a display panel and a display apparatus. The display panel includes: a base substrate including a notch area, a display area and a first non-display area between the notch area and the display area; a first conductive layer on the base substrate; a target insulating layer between the first conductive layer and the base substrate; and a functional layer between the target insulating layer and the base substrate. The display area includes a plurality of sub-pixels, and at least one of the plurality of sub-pixels includes a connecting through hole, wherein the connecting through hole runs through the target insulating layer, and the first conductive layer is electrically connected to the functional layer by the connecting through hole. The first non-display area includes at least one auxiliary through hole which runs through the target insulating layer and is not filled with a conductive material. US 2023/351958 A1 further discloses an array substrate, a display panel including the array substrate and a display device. SUMMARY It is an object of the present invention to provide a display substrate and a display device. The object is achieved by the features of claim 1. Further embodiments are defined in the corresponding dependent claims. Even though the description refers to embodiments or to the invention, it is to be understood that the invention is defined by the claims and embodiments of the invention are those comprising at least all the features of claim 1. BRIEF DESCRIPTION OF THE DRAWINGS In order to clearly illustrate the technical solution of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described. FIG. 1A is a schematic diagram of a sub-pixel in a display substrate provided by at least one embodiment of the present disclosure.FIG. 1B is a schematic circuit diagram of a sub-pixel in a display substrate provided by at least one embodiment of the present disclosure.FIG. 2 is a schematic layout diagram of a pixel circuit provided by at least one embodiment of the present disclosure.FIG. 3A is a schematic diagram of a first active layer provided by at least one embodiment of the present disclosure.FIG. 3B is a s