Search

EP-4518628-B1 - DISPLAY PANEL

EP4518628B1EP 4518628 B1EP4518628 B1EP 4518628B1EP-4518628-B1

Inventors

  • CHEON, SOOHONG

Dates

Publication Date
20260513
Application Date
20240822

Claims (15)

  1. A display panel comprising: data lines (DL1 to DLm) arranged on a base layer, spaced apart from one another in a first direction, and each extending in a second direction intersecting the first direction; and a unit pixel electrically connected to the data lines and including a first pixel (PX-R), a second pixel (PX-G), and a third pixel (PX-B) each configured to provide a light to a pixel area, wherein the first pixel (PX-R) includes: a common electrode (CP) including a first lower electrode (C1-1), a light shielding pattern, and a second lower electrode (C1-2) sequentially arranged in the second direction; a first upper electrode (C2-1) overlapping the first lower electrode and configured to a first capacitor with the first lower electrode; a second upper electrode (C2-2) overlapping the second lower electrode and configured to a second capacitor with the second lower electrode; a first transistor (T1-R) including: an active pattern (A1-R) overlapping the light shielding pattern; and a gate electrode (GP) overlapping the active pattern; and a light emitting element (OLED-R) electrically connected to the first transistor, and an end of the gate electrode (GP) is electrically connected to the first upper electrode (C2-1), and another end of the gate electrode (GP), which is spaced apart from the end in the second direction, is electrically connected to the second upper electrode.
  2. The display panel of claim 1, further comprising: a first insulating layer (10) disposed on the base layer and covering the common electrode; a second insulating layer (20) disposed on the first insulating layer (10) and covering the first upper electrode (C2-1) and the second upper electrode (C2-2); and a third insulating layer (30) disposed on the second insulating layer (20), wherein the end of the gate electrode is electrically connected to the first upper electrode (C2-1) through a first contact hole defined in the second insulating layer (20), and the another end of the gate electrode is electrically connected to the second upper electrode through a second contact hole defined in the second insulating layer (20).
  3. The display panel of claim 1 or 2, wherein the active pattern (A1-R), the first upper electrode (C2-1), and the second upper electrode (C2-2) are disposed on a same layer.
  4. The display panel of any of the preceding claims, wherein the active pattern (A1-R) is disposed between the first upper electrode (C2-1) and the second upper electrode (C2-2) in the second direction.
  5. The display panel of any of the preceding claims, wherein the first pixel (PX-R) further includes a second transistor (T2-R) and a third transistor (T3-R) each including an active pattern (A2-R, A3-R) and a gate electrode (GP).
  6. The display panel of claim 5, wherein each of the second pixel (PX-G) and the third pixel (PX-B) includes a capacitor, a first transistor (T1-G, T1-B), a second transistor (T2-G, T2-B), and a third transistor (T3-G, T3-B) each including an active pattern and a gate electrode (GP), and a light emitting element.
  7. The display panel of any of the preceding claims, wherein the light emitting element included in each of the first pixel (PX-R), the second pixel (PX-G), and the third pixel (PX-B) includes a first electrode, a second electrode, and a light emitting layer disposed between the first electrode and the second electrode.
  8. The display panel of any of the preceding claims, further comprising: a pixel defining film (PDL) in which openings exposing at least portions of the first electrodes of the unit pixel are defined, wherein the pixel area of each of the first pixel, the second pixel, and the third pixel is defined by a corresponding one of the openings.
  9. The display panel of claim 8, wherein the pixel area of the first pixel is spaced apart from the pixel area of the third pixel in the second direction, and the pixel area of the second pixel is spaced apart from the pixel areas of the first pixel and the third pixel in a diagonal direction intersecting the first direction and the second direction intersecting the first direction.
  10. The display panel of claim 9, wherein the first pixel, the second pixel, and the third pixel provide a same light.
  11. The display panel of claim 10, wherein an area of the pixel area of the first pixel is smaller than an area of the pixel area of the second pixel and larger than an area of the pixel area of the third pixel.
  12. The display panel of claim 10, wherein at least a portion of the gate electrode (GP) overlaps the pixel area of the first pixel.
  13. The display panel of claim 6, wherein among the data lines, a first data line electrically connected to the first pixel is spaced apart from a second data line electrically connected to the second pixel in the first direction, with the active patterns of the first and second transistors disposed between the first and second data lines, and a third data line electrically connected to the third pixel and the first data line are spaced apart from each other in the first direction, with the second data line disposed between the third and first data lines.
  14. The display panel of claim 13, further comprising: light shielding patterns overlapping the active pattern included in the second pixel and the active pattern included in the third pixel and spaced apart from each other in the second direction.
  15. The display panel of claim 14, wherein the light shielding patterns are arranged between the first data line, the second data line, and the third data line.

Description

BACKGROUND Embodiments of the disclosure relate to a display panel and to a display panel including a circuit element having improved reliability. A display panel includes pixels and a driving circuit (e.g., a scan driving circuit and a data driving circuit) that controls the pixels. Each of the pixels includes a display element and a pixel driving circuit that controls the display element. The pixel driving circuit may include organically connected transistors and at least one capacitor. US2023247878A1 and US2023141774A1 disclose driving circuits of display panels comprising transistors and at least one capacitor. SUMMARY Embodiments of the disclosure provide a display panel having improved display quality. According to the present claimed invention, a display panel includes a base layer, data lines arranged on the base layer, spaced apart from each other in a first direction, and each extending in a second direction intersecting the first direction, and a unit pixel electrically connected to the data lines and including a first pixel, a second pixel, and a third pixel that each provide a light to a pixel area, wherein the first pixel includes a common electrode including a first lower electrode, a light shielding pattern, and a second lower electrode sequentially arranged in the second direction, a first upper electrode that overlaps the first lower electrode and forms a first capacitor with the first lower electrode, a second upper electrode that overlaps the second lower electrode and forms a second capacitor with the second lower electrode, a first transistor including an active pattern overlapping the light shielding pattern and a gate electrode overlapping the active pattern, and a light emitting element electrically connected to the first transistor, and an end of the gate electrode is electrically connected to the first upper electrode, and another end of the gate electrode, which is spaced apart from the end in the second direction, is electrically connected to the second upper electrode. The display panel may further include a first insulating layer that is disposed on the base layer and covers the common electrode, a second insulating layer that is disposed on the first insulating layer and covers the first upper electrode and the second upper electrode, and a third insulating layer disposed on the second insulating layer, wherein the end of the gate electrode may be electrically connected to the first upper electrode through a first contact hole defined in the second insulating layer, and the another end of the gate electrode may be electrically connected to the second upper electrode through a second contact hole defined in the second insulating layer. The active pattern, the first upper electrode, and the second upper electrode may be disposed on a same layer. The active pattern may be disposed between the first upper electrode and the second upper electrode in the second direction. The first pixel may further include a second transistor and a third transistor each including an active pattern and a gate electrode. Each of the second pixel and the third pixel may include a capacitor, a first transistor, a second transistor, and a third transistor each including an active pattern and a gate electrode, and a light emitting element. The light emitting element included in each of the first pixel, the second pixel, and the third pixel may include a first electrode, a second electrode, and a light emitting layer disposed between the first electrode and the second electrode. The display panel may further include a pixel defining film in which openings exposing at least portions of the first electrodes of the unit pixel are defined, wherein the pixel area of each of the first pixel, the second pixel, and the third pixel may be defined by a corresponding one of the openings. The pixel area of the first pixel may be spaced apart from the pixel area of the third pixel in the second direction, and the pixel area of the second pixel may be spaced apart from the pixel areas of the first pixel and the third pixel in a diagonal direction intersecting the first direction and the second direction intersecting the first direction. The first pixel, the second pixel, and the third pixel may provide a same light. An area of the pixel area of the first pixel may be smaller than an area of the pixel area of the second pixel and larger than an area of the pixel area of the third pixel. At least a portion of the gate electrode may overlap the pixel area of the first pixel. Among the data lines, a first data line electrically connected to the first pixel may be spaced apart from a second data line electrically connected to the second pixel in the first direction, with the active patterns of the first and second transistors disposed between the first and second data lines, and a third data line electrically connected to the third pixel and the first data line are spaced apart from each other in the first direction, with