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EP-4525557-B1 - POWER SUPPLY CIRCUIT, RELATED SYSTEM AND METHOD

EP4525557B1EP 4525557 B1EP4525557 B1EP 4525557B1EP-4525557-B1

Inventors

  • POLISI, VINCENZO
  • TAGLIAVIA, DONATO
  • TRECARICHI, CALOGERO ANDREA
  • DONDINI, MIRKO

Dates

Publication Date
20260513
Application Date
20240829

Claims (12)

  1. A power supply circuit (1a) comprising: - a plurality of output terminals (OUT 1 -OUT k ); - for each output terminal (OUT 1 -OUT k ) a respective current supply circuit (12 1 -12 k ), wherein each current supply circuit (12 1 -12 k ) is configured to provide an output current ( i 1 -i k ) to the respective output terminal (OUT 1 -OUT k ) as a function of a respective first digital control signal (Curr_Set_CH1-Curr_Set_CHk), and wherein each current supply circuit (12 1 -12 k ) comprises a current sensor (122) configured to provide a measurement current ( i MON1 -i MONk ) being proportional to the respective output current ( i 1 -i k ); - a first multiplexer circuit (184) configured to provide a selected measurement current ( i MONi ) by selecting one of the measurement currents ( i MON1 -i MONk ) as a function of a selection signal (SEL) indicating a selected current supply circuit (12 1 -12 k ); characterized in that said power supply circuit (1a) further comprises: - a second multiplexer circuit (186) configured to provide a selected digital control signal (Curr_Set_CHi) by selecting one of the first digital control signals (Curr_Set_CH1-Curr_Set_CHk) as a function of said selection signal (SEL) indicating a selected current supply circuit (12 1 -12 k ); - a comparison circuit (180) configured to: - generate a threshold current ( i TH ) as a function of one or more digital threshold control signals (TH), - compare the selected measurement current ( i MONi ) with said threshold current ( i TH ), - in response to determining that said selected measurement current ( i MONi ) is greater than said threshold current ( i TH ), de-assert a comparison signal (COMP), and - in response to determining that said selected measurement current ( i MONi ) is smaller than said threshold current ( i TH ), assert said comparison signal (COMP); - a control circuit (182) configured to repeat the following operations periodically: - generate said selection signal (SEL) in order to select a measurement current ( i MONi ) and a first digital control signal (Curr_Set_CHi) associated with a given current supply circuit (12 1 -12 k ); - generate said one or more digital threshold control signals (TH) as a function of said selected digital control signal (Curr_Set_CHi) in order to: - during a first phase (PH1), set via said comparison circuit (180) said threshold current ( i TH ) to a first value ( i TH1 ), said first value ( i TH1 ) being smaller than an expected value ( i MONi,exp ) for said selected measurement current ( i MONi ) as indicated by said selected digital control signal (Curr_Set_CHi), and - during a second phase (PH2), set via said comparison circuit (180) said threshold current ( i TH ) to a second value ( i TH2 ), said second value ( i TH2 ) being greater than said expected value ( i MONi,exp ) for said selected measurement current ( i MONi ) as indicated by said selected digital control signal (Curr_Set_CHi), - verify whether said comparison signal (COMP) is de-asserted during said first phase (PH1) and asserted during said second phase (PH2), - in response to determining that said comparison signal (COMP) is de-asserted during said first phase (PH1) and asserted during said second phase (PH2), assert a status signal (STATUSi), and - in response to determining that said comparison signal (COMP) is asserted during said first phase (PH1) or de-asserted during said second phase (PH2), de-assert said status signal (STATUSi).
  2. The power supply circuit according to Claim 1, where each current supply circuit (12 1 -12 k ) comprises: - a current digital-to-analog converter (1200) configured to receive a first reference current ( i REF ) and the respective first digital control signal (Curr_Set_CH1- Curr_Set_CHk), wherein said first digital control signal (Curr_Set_CH1-Curr_Set_CHk) is indicative of a first multiplier, and said current digital-to-analog converter (1200) is configured to generate a first current ( i SET ) by multiplying said first reference current ( i REF ) with said first multiplier; and - a scaling circuit (1204) configured to generate said output current ( i 1 -i k ) by generating an amplified version of said first current ( i SET ) according to a first scaling factor.
  3. The power supply circuit according to Claim 2, wherein the scaling circuit (1204) of each current supply circuit (12 1 -12 k ) comprises a first Field-Effect Transistor, FET, (1212) connected between a regulated voltage ( V REG ) and the respective output terminal (OUT 1 -OUT k ), and wherein the current sensor (122) of each current supply circuit (12 1 -12 k ) comprises a second FET (1222) configured to provide the measurement current ( i MON ) of the current supply circuit (12 1 -12 k ), wherein said second FET (1222) is a scaled version of said first FET (1212) according to a second scaling factor and the current supply circuit (12 1 -12 k ) is configured such that the gate-source voltage of said second FET (1222) corresponds to the gate-source voltage of said first FET (1212).
  4. The power supply circuit according to Claim 3, wherein the ratio between said first scaling factor and said second scaling factor is one.
  5. The power supply circuit according to Claim 3 or Claim 4, wherein each current supply circuit (12 1 -12 k ) comprises: - a first resistance (1206) connected between said regulated voltage ( V REG ) and an output of said current digital-to-analog converter (1200); - a second resistance (1208) connected in series with the current path of said first FET (1212) between said regulated voltage ( V REG ) and the respective output terminal (OUT 1 -OUT k ), - an operational amplifier (1210) configured to drive the gate-source voltage of said first FET (1212) such that the voltage-drop at said second resistance (1208) corresponds to the voltage-drop at said first resistance (1206); - a third resistance (1220) connected in series with the current path of said second FET (1222) to said regulated voltage (V REG ), wherein the gate terminal of said second FET (1222) is connected to the gate terminal of said first FET (1212).
  6. The power supply according to any of the previous claims, wherein said one or more digital threshold control signals (TH) comprise a second digital control signal (Curr_Set_TH), and wherein said comparison circuit (180) comprises: - a further current digital-to-analog converter (1800) configured to receive a second reference current ( i REF ' ) and said second digital control signal (Curr_Set_TH), wherein said second digital control signal (Curr_Set_TH) is indicative of a second multiplier, and said further current digital-to-analog converter (1800) is configured to generate said threshold current ( i TH ) by multiplying said second reference current ( i REF ') with said second multiplier.
  7. The power supply circuit according to Claim 6, wherein said control circuit (182) is configured to: - during said first phase (PH1), set said second digital control signal (Curr_Set _TH) to a first value being smaller than said selected digital control signal (Curr_Set_CHi) by a given first percentage, and - during said second phase (PH2), set said second digital control signal (Curr_Set _TH) to a second value being greater than said selected digital control signal (Curr_Set_CHi) by a given second percentage.
  8. The power supply circuit according to Claim 6, wherein said one or more digital threshold control signals (TH) comprise a reference current selection signal (CTH), and wherein said control circuit (182) is configured to: - during said first phase (PH1), set said second digital control signal (Curr_Set_TH) to the value of said selected digital control signal (Curr_Set_CHi) and select (SREF) via said reference current selection signal (CTH) as said second reference current ( i REF ' ) a current ( i REFA ) having a value being smaller than said first reference current ( i REF ) by a given first percentage, and - during said second phase (PH2), set said second digital control signal (Curr_Set_TH) to the value of said selected digital control signal (Curr_Set_CHi) and select (SREF) via said reference current selection signal (CTH) as said second reference current ( i REF ' ) a current (i REFB ) having a value being greater than said first reference current ( i REF ) by a given second tolerance percentage.
  9. The power supply according to any of the previous claims, wherein said comparison circuit (180) comprises: - a summation node (B) configured to provide a current ( i M ) corresponding to the difference between said selected measurement current ( i MONi ) and said threshold current ( i TH ); - a current comparator (1804) configured to: - in response to determining that said current ( i M ) is greater than zero, de-assert said comparison signal (COMP), and - in response to determining that said current ( i M ) is smaller than zero, assert said comparison signal (COMP).
  10. The power supply according to any of the previous claims 1 to 8, wherein said comparison circuit (180) comprises: - a first measurement resistance (Rmon1) configured to be transversed by said threshold current ( i TH ); - a second measurement resistance (Rmon2) configured to be transversed by said selected measurement current ( i MONi ); - a voltage comparator (1806) configured to: - in response to determining that a voltage-drop at said first measurement resistance (Rmon1) is greater than a voltage-drop at said second measurement resistance (Rmon2), assert said comparison signal (COMP), - in response to determining that the voltage-drop at said first measurement resistance (Rmon1) is smaller than the voltage-drop at said second measurement resistance (Rmon2), de-assert said comparison signal (COMP).
  11. A system comprising a power supply circuit (1a) according to any of the previous claims, and at least one load (20) connected to the output terminals (OUT 1 -OUT k ) of said power supply circuit (1a).
  12. A method of operating a power supply circuit (1a) according to any of the previous claims 1 to 10, comprising: - generating said first digital control signals (Curr_Set_CH1-Curr_Set_CHk), whereby said current supply circuits (12 1 -12 k ) provide said output currents ( i 1 -i k ); - generating said selection signal (SEL) in order to select via said first multiplexer circuit (184) a measurement current ( i MONi ) and via said second multiplexer circuit (186) a first digital control signal (Curr_Set_CHi) associated with a given current supply circuit (12 1 -12 k ); - generating said one or more digital threshold control signals (TH) as a function of said selected digital control signal (Curr_Set_CHi) in order to: - during a first phase (PH1), setting via said comparison circuit (180) said threshold current ( i TH ) to a first value ( i TH1 ), said first value ( i TH1 ) being smaller than an expected value ( i MONi,exp ) for said selected measurement current ( i MONi ) as indicated by said selected digital control signal (Curr_Set_CHi), and - during a second phase (PH2), setting via said comparison circuit (180) said threshold current ( i TH ) to a second value ( i TH2 ), said second value ( i TH2 ) being greater than said expected value ( i MONi,exp ) for said selected measurement current ( i MONi ) as indicated by said selected digital control signal (Curr_Set_CHi), - verifying whether said comparison signal (COMP) generated by said comparison circuit (180) is de-asserted during said first phase (PH1) and asserted during said second phase (PH2), - in response to determining that said comparison signal (COMP) is de-asserted during said first phase (PH1) and asserted during said second phase (PH2), asserting a status signal (STATUSi), and - in response to determining that said comparison signal (COMP) is asserted during said first phase (PH1) or de-asserted during said second phase (PH2), de-asserting said status signal (STATUSi).

Description

Technical field The embodiments of the present description refer to power supply circuits, such as power supply circuits configured to supply lighting modules. Description of the relevant art Figure 1 shows a typical lighting system. The lighting system includes a power supply circuit 1 and one or more lighting modules 20, such as lighting modules 201 to 20k. For example, the lighting modules 20 may form a LED or OLED panel 2. In the example considered, each lighting module 20 includes one or more lighting sources. For example, in the example considered, each lighting module 20 including at least one LED (Light Emitting Diode) or OLED (organic light-emitting diode) L. For example, often each lighting module 20 includes a LED string, i.e., a plurality of LEDs connected in series, as schematically shown via two LEDs L1 and L2 connected in series. The person skilled in the art will appreciate that a LED (or a LED chain) is usually not supplied with a constant voltage but rather via a current. Accordingly, in order to individually control the light intensity of each lighting module 20, the power supply circuit 1 usually comprises for each lighting module 20 a respective output terminal or channel OUT, such as output terminals OUT1 to OUTk, and the power supply circuit 1 is configured to provide to each output terminal OUT a respective current, such as currents i1 to ik. Such power supply circuits 1 are well-known in the art. For example, the applicant of the present patent application sells LED driver integrated circuits, such as the L99LDLH32 having 32 channels. For example, the operation of the L99LDLH32 is described in the datasheet DS12879, "L99LDLH32 - 32-channel LED driver with automotive CAN FD Light interface," e.g., revision 5 of 2021. In many applications, the power supply circuit 1 should be able to monitor each of the currents i1 to ik. For example, such a monitoring may be useful in order to verify whether each current provided by the power supply circuit 1 corresponds to an expected value or more generally is within an expected tolerance range, which, e.g., permits to determine whether the intensity of the light emitted by a lighting module 20 correspond to an expected value and/or whether a lighting module represents a malfunction, e.g., due to a short-circuit or open-load condition. Accordingly, the present invention relates to a power supply circuit according to the preamble of Claim 1, which is known, e.g. from document US 9,451,664 B2. Document US 10,893,591 B2 may also be of interest for the present application. Object and summary Considering the foregoing, an object of various embodiments of the present disclosure is to provide solutions for verifying the current supply conditions of a power supply circuit. According to one or more embodiments, the above object is achieved by a power supply circuit having the distinctive elements set forth specifically in the ensuing claims. The embodiments moreover concern a related system and method. The claims form an integral part of the technical teaching of the description provided herein. As mentioned before, various embodiments of the present disclosure relate to a power supply circuit. In various embodiments, the power supply circuit comprises a plurality of output terminals, such as pads or pins of a respective integrated circuit comprising the power supply circuit, and for each output terminal a respective current supply circuit. Specifically, each current supply circuit is configured to provide an output current to the respective output terminal as a function of a respective first digital control signal. For example, in various embodiments, each current supply circuit comprises a current digital-to-analog converter configured to receive a first reference current and the respective first digital control signal, wherein the first digital control signal is indicative of a first multiplier, and the current digital-to-analog converter is configured to generate a first current by multiplying the first reference current with the first multiplier. Moreover, each current supply circuit comprises a scaling circuit configured to generate the output current by generating an amplified version of the first current according to a first scaling factor. For example, in various embodiments each current supply circuit comprises a first resistance connected between a regulated voltage and an output of the current digital-to-analog converter, a second resistance connected with the current path of the first FET between the regulated voltage and the respective output terminal, and an operational amplifier configured to drive the gate-source voltage of the first FET such that the voltage-drop at the second resistance corresponds to the voltage-drop at the first resistance. Accordingly, in this case, the ratio between the resistance value of the second resistance and the resistance value of the first resistance defines the first scaling factor. In various embodiments, e