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EP-4529679-B1 - DDR PHY FLOORPLAN

EP4529679B1EP 4529679 B1EP4529679 B1EP 4529679B1EP-4529679-B1

Inventors

  • KANDUKURI, Praveen Kumar
  • TORVI, PAVAN VITHAL

Dates

Publication Date
20260506
Application Date
20230509

Claims (5)

  1. An integrated circuit, IC, comprising: a first set of core logic (212) configured to convert data between a single data rate and a double data rate; a first data input or output, I/O, block (202) on a first side of the first set of core logic, the first data I/O block interfacing with the first set of core logic, the first data I/O block including a plurality of I/O circuits for interfacing with a dynamic random-access memory, DRAM, (110) the first data I/O block being in one column; a second set of core logic (214) configured to process command and address, CA, information; a first CA I/O subblock (206) on a second side of the first set of core logic, the first CA I/O subblock interfacing with the second set of core logic, the first CA I/O subblock including a plurality of I/O circuits for interfacing with the DRAM; the integrated circuit, IC, characterized in that it further comprises: a first set of power switches (218) adjacent at least one side of the first CA I/O subblock, the first set of power switches being coupled to the first set of core logic and the second set of core logic, wherein the first set of power switches is immediately adjacent the at least one side of the first CA I/O subblock; a third set of core logic (216) configured to convert data between a single data rate and a double data rate; a second data I/O block (204) on a first side of the third set of core logic, the second data I/O block interfacing with the third set of core logic, the second data I/O block including a plurality of I/O circuits for interfacing with the DRAM, the second data I/O block being in one column; a second CA I/O subblock (208) on a second side of the third set of core logic, the second CA I/O subblock interfacing with the second set of core logic, the second CA I/O subblock including a plurality of I/O circuits for interfacing with the DRAM, the first CA I/O subblock and the second CA I/O subblock together being a folded double-column I/O block; and a second set of power switches (220) adjacent at least one side of the second CA I/O subblock, the second set of power switches being coupled to the third set of core logic and the second set of core logic, wherein the second set of power switches is immediately adjacent the at least one side of the second CA I/O subblock. a phase-locked loop, PLL, (210) on a first side of the second set of core logic and between the first CA I/O subblock and the second CA I/O subblock, the PLL being configured to provide a clock signal to the first set of core logic, the second set of core logic, and the third set of core logic, wherein a clock path (222) length for carrying the clock signal between the PLL and the first set of core logic is approximately equal to a clock path length for carrying the clock signal between the PLL and the third set of core logic; and at least one bank of decoupling capacitors adjacent one of the first data I/O block, the first CA I/O subblock, the second CA I/O subblock, or the second data I/O block.
  2. The IC of claim 1, wherein the first set of power switches is adjacent two sides of the first CA I/O subblock, and at least a portion of the first set of power switches is between the first CA I/O subblock and the first set of core logic.
  3. The IC of claim 1, wherein the second set of power switches is adjacent two sides of the second CA I/O subblock, and at least a portion of the second set of power switches is between the second CA I/O subblock and the third set of core logic.
  4. The IC of claim 1, wherein the at least one bank of decoupling capacitors is adjacent each of the first data I/O block, the first CA I/O subblock, the second CA I/O subblock, and the second data I/O block.
  5. The IC of claim 1, wherein the IC is a double data rate, DDR, physical, PHY, block.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims the benefit of U.S. Patent Application Serial No. 17/664,567, entitled "DDR PHY FLOORPLAN" and filed on May 23, 2022. TECHNICAL FIELD The present disclosure relates generally to a layout structure, and more particularly, to a double data rate (DDR) physical (PHY) floorplan. INTRODUCTION A double data rate (DDR) physical (PHY) provides an interface between a memory controller and a dynamic random-access memory (DRAM). There is currently a need to reduce power consumption, increase performance, and reduce a footprint area for DDR PHYs. Attention is drawn to US 2007/028013 A1 describing a semiconductor device that includes a first semiconductor chip, and a second semiconductor chip which includes a high-speed serial I/F circuit which transfers serial data between the high-speed serial I/F circuit and an external device through a serial bus and is stacked on the first semiconductor chip. A pad region in which pads (electrodes) for connecting the external device and the high-speed serial I/F circuit are disposed is provided along a first side of the second semiconductor chip which is the short side. A pad region in which pads for connecting an internal circuit included in the first semiconductor chip and the high-speed serial I/F circuit are disposed is provided along a second side of the second semiconductor chip which is the long side. BRIEF SUMMARY The present invention is set forth in the independent claim. Further embodiments of the invention are described in the dependent claims. In an aspect of the disclosure, an integrated circuit (IC) includes a first set of core logic configured to convert data between a single stream and a double stream. The IC further includes a first data input or output (I/O) block on a first side of the first set of core logic. The first data I/O block interfaces with the first set of core logic. The first data I/O block includes a plurality of I/O circuits for interfacing with a DRAM. The first data I/O block is in one column. The IC further includes a second set of core logic configured to process command and address (CA) information. The IC further includes a first CA I/O subblock on a second side of the first set of core logic. The first CA I/O subblock interfaces with the second set of core logic. The first CA I/O subblock includes a plurality of I/O circuits for interfacing with the DRAM. The IC further includes a first set of power switches adjacent at least one side of the first CA I/O subblock. The first set of power switches is coupled to the first set of core logic and the second set of core logic. In one configuration, the IC further includes a third set of core logic configured to convert data between a single stream and a double stream. In the configuration, the IC further includes a second data I/O block on a first side of the third set of core logic. The second data I/O block interfaces with the third set of core logic. The second data I/O block includes a plurality of I/O circuits for interfacing with the DRAM. The second data I/O block is in one column. In the configuration, the IC further include s a second CA I/O subblock on a second side of the third set of core logic. The second CA I/O subblock interfaces with the second set of core logic. The second CA I/O subblock includes a plurality of I/O circuits for interfacing with the DRAM. The first CA I/O subblock and the second CA I/O subblock together are a folded double-column I/O block. In the configuration, the IC further includes a second set of power switches adjacent at least one side of the second CA I/O subblock. The second set of power switches is coupled to the third set of core logic and the second set of core logic. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram illustrating a DDR PHY interfacing between a memory controller and a DRAM.FIG. 2 is a diagram illustrating a first configuration of a DDR PHY floorplan.FIG. 3 is a diagram illustrating a second configuration of a DDR PHY floorplan. DETAILED DESCRIPTION The detailed description set forth below in connection with the appended drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well known structures and components are shown in block diagram form in order to avoid obscuring such concepts. Apparatuses and methods will be described in the following detailed description and may be illustrated in the accompanying drawings by various blocks, modules, components, circuits, steps, processes, algorithms, elements, etc. FIG. 1 is a diagram 100 illustrating a DDR PHY 106 (also referred to as a DDR P