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EP-4535411-B1 - A METHOD FOR THINNING A SEMICONDUCTOR SUBSTRATE

EP4535411B1EP 4535411 B1EP4535411 B1EP 4535411B1EP-4535411-B1

Inventors

  • BEYNE, ERIC
  • WITTERS, LIESBETH

Dates

Publication Date
20260506
Application Date
20231006

Claims (7)

  1. A method for producing a thinned semiconductor substrate, comprising the following consecutively performed steps : - providing a first substrate (1) having a planar front side and a planar back side, the first substrate being integrally formed of a crystalline semiconductor material or comprising on its front side a layer that is integrally formed of said crystalline semiconductor material, - producing a device layer (20) on the front side of the first substrate (1), said device layer comprising a plurality of semiconductor devices, - producing additional layers (21) on top of the device layer (20), ending with a layer having a planar top surface (22), - permanently or temporarily bonding the first substrate (1) to a second substrate (23) by bonding said planar top surface (22) to a bonding surface of the second substrate (23), - thinning the first substrate (1) from the back side thereof, wherein, - before producing the device layer (20), and in at least one or more areas of the first substrate (1) wherein said semiconductor devices are to be produced, cavities (10) are produced through the front surface of the first substrate and into the crystalline semiconductor material of the first substrate, and said cavities are filled at least partially with a dielectric material, to thereby form dielectric-filled cavities (14), - the devices in said one or more areas are produced in a plurality of regions located between two adjacent dielectric-filled cavities (14), and said devices are covered by an additional dielectric layer (17), - at the end of the thinning step, the first substrate is reduced to a uniform layer (1') of the crystalline semiconductor material remaining above said dielectric-filed cavities (14), - after the thinning step, the crystalline semiconductor material is subjected to an anisotropic etch process, - the in-plane dimensions of said regions located between two adjacent dielectric-filled cavities (14) and the depth of said adjacent cavities (14) are configured so that the anisotropic etch process stops on one or more of the following, without reaching the semiconductor devices : o on crystallographic planes of the crystalline semiconductor material, o on the dielectric material in the cavities (14), o on said additional dielectric layer (17), - the method further comprises the following steps, after the anisotropic etch process : o depositing a further dielectric material (30) on the thinned back side of the first substrate (1), o planarizing said further dielectric material (30) and remaining portions of the crystalline semiconductor material to a common planarized surface (31).
  2. The method according to claim 1, wherein additional dielectric-filled cavities (40) are also produced in areas of the first substrate (1) wherein no semiconductor devices are to be produced.
  3. The method according to claim 2, wherein the spacing between any adjacent pair of said additional dielectric-filled cavities (40) is configured so that the anisotropic etch process does not reach the front side of the first substrate (1) in said spacing.
  4. The method according to any one of the preceding claims, wherein at least some of the dielectric-filled cavities (14) in said one or more areas of the first substrate (1) wherein said semiconductor devices are to be produced, are shallow trench isolation regions.
  5. The method according to any one of the preceding claims, wherein the crystalline semiconductor material is crystalline silicon.
  6. The method according to claim 5, wherein the first substrate is a silicon process wafer having planar front and back sides oriented along the (100) crystallographic of silicon.
  7. The method according to any one of the preceding claims, wherein said in-plane dimensions and the depths of the dielectric-filled cavities (14) are configured so that at least in some of said regions between two adjacent dielectric-filled cavities, the etch process ends when a V-shaped groove (26) is formed in the material of the first substrate (1).

Description

Field of the Invention The present invention is related to semiconductor processing, in particular to the extreme thinning of a substrate from the backside. State of the art In semiconductor processing, active devices such as transistors and diodes are fabricated on the front side of a semiconductor substrate, such as a Si process wafer of 300 mm in diameter. On top of the devices, a multilayer interconnect structure is built, for routing signals to and from the devices. Traditionally, the delivery of power to the devices was also routed through this front side interconnect structure. However recent development has led to the integration of a back side power delivery network, built on the backside of the substrate. To realize this, extreme thinning of the substrate from the backside is required, to bring the substrate portion to a thickness of less than 500 nm, preferably even to the point of completely removing the Si substrate, leaving only the active Si devices. Also in stacked IC configurations, the substrate portion of IC chips needs to be thinned to similar extremely low thickness values. Traditionally, thinning takes place by bonding the wafer face down to another process wafer or to a temporary carrier substrate, and removing the bulk of the wafer from the back side thereof, by applying grinding and polishing techniques. A problem however is that no process wafer is perfectly flat. Standard 300mm diameter process wafers have a typical thickness of 775µm with a total thickness variation (TTV) of only 1 or a few micrometres. At full thickness this is a relative precision better than 0.2%. After wafer-to-wafer bonding, both the wafer that is to be thinned and the receiving (supporting) wafer are subject to such a thickness variation. Therefore, thinning a wafer from the backside to extremely low thickness values by grinding and polishing techniques alone is virtually impossible without negatively affecting the active devices in one or more areas of the wafer. When thinning down the wafer thickness to less than a few micrometres, the few micrometre TTV variations dominate the problem. A known solution to this problem is the production of ICs on a so-called SOI wafer (silicon-on-insulator), which comprises a thin oxide layer on the bulk silicon, and a thin epitaxially grown Si layer on top of the oxide. The devices and the multilayer interconnect structure are fabricated on this epitaxial Si layer, after which the wafer is bonded face down to another wafer or a carrier. Thinning from the back side by grinding and polishing is then stopped prior to reaching the oxide layer and the remaining bulk silicon is removed by wet etching, wherein the oxide layer acts as an etch stop layer. Thereafter the oxide itself is removed by etching selectively with respect to the epitaxially grown Si. Instead of an oxide layer, an epitaxially grown SiGe layer can be used as an etch stop layer. These solutions are however technically complex and thereby increase the cost of the semiconductor fabrication process. As an example, documents US 2017/084628 A1 and US 2018/145030 A1 disclose processes comprising a step of thinning an initial substrate using STI regions as an etch stop and the document US 10354980 B1 discloses a process of thinning an initial substrate using a conductive layer as an etch stop layer. Summary of the invention The invention is related to a method in accordance with the appended claims. According to the method, a first crystalline semiconductor substrate is provided and a layer of semiconductor devices is produced on the front side thereof, in regions separated by dielectric-filled cavities, which may include shallow trench isolation regions, formed prior to the device processing. Additional layers such as the layers of a multilayer interconnect structure are formed on the device layer. The substrate is then flipped and bonded face down to a second substrate, following by the thinning of the crystalline first substrate from the back side. The thinning proceeds as far as possible without removing the full thickness of the first substrate anywhere across its surface, i.e. taking into account any intrinsic thickness variation of the first and second substrates. After this, an anisotropic etch is performed for removing additional material of the first substrate. In accordance with the invention, the in-plane dimensions of the device regions separated by the dielectric-filled cavities are configured so that the anisotropic etch is stopped by a crystallographic plane of the substrate material or by the dielectric material in said cavities, before it can reach said devices on the front side. Depending on the exact dimensions of the device regions and on possible depth differences between adjacent dielectric-filled cavities, the anisotropic etch may stop when a V-shaped groove is formed in the substrate material. After the anisotropic etch, a further dielectric material is deposited and planarized, along with r