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EP-4540823-B1 - DEVICE WITH RECONFIGURABLE SHORT TERM DATA RETENTION

EP4540823B1EP 4540823 B1EP4540823 B1EP 4540823B1EP-4540823-B1

Inventors

  • SYED, Ghazi Sarwat
  • SEBASTIAN, ABU

Dates

Publication Date
20260513
Application Date
20230612

Claims (12)

  1. A device (900) comprising a plurality of resistive phase change elements (901), the plurality of resistive, phase change elements comprising a resistive, phase change material (1103, 1112, 1122, 1132), the device being configured to: apply programming pulses to a subset of the plurality of resistive elements to a set of second binary states with different retention periods (1001:1006) to provide temporary resistance changes of the subset from a respective first resistance state corresponding to a first binary state to a respective second resistance state corresponding to a second binary state, the respective temporary resistances of the resistive material of the subset changed for respective predefined retention periods, wherein providing the resistance changes comprises performing a temporary amorphization of the phase change material, thereby creating a set of amorphous volumes (1103a, 111a2, 1122a, 1132a), wherein the device is configured such that respective resistances of the resistive material of the subset of the plurality of resistive elements reverts automatically after the respective predefined retention periods from the respective second resistance state to the respective first resistance state by a crystallization of the respective amorphous volumes, thereby automatically deleting the respective second binary states, wherein the device is configured to tune the respective predefined retention periods of the plurality of resistive elements by programming the subset of the plurality of resistive elements to a plurality of different amorphous volumes.
  2. The device according to claim 1, wherein the resistive material is selected from the group consisting of: Sb, Ge x Sb y , Ga x Sb y , Sb x Te y , Ge x Sb y Te z , Ge x Te y and Ag x In y Sb z Te n , wherein x, y, z, and n represent atomic percentages.
  3. The device according to claim 2, wherein the resistive material is doped with a material selected from the group consisting of: O, N, C, SiO 2 , and Sc.
  4. The device according to claim 1, wherein the device is configured to operate in an environment having an elevated temperature above room temperature.
  5. The device according to claim 4, wherein the elevated temperature is in a temperature range between 25°C and 100° C.
  6. The device according to claim 1, wherein the predefined retention periods are in a range between 1 µs to 12 hours.
  7. The device according to claim 1, wherein the device is embodied as a computational memory device.
  8. The device according to claim 1, wherein the device is embodied as a short-term memory device.
  9. The device according to claim 1, wherein a geometry of the plurality of resistive elements is selected from the group consisting of: a bridge cell, a mushroom cell, a trench cell, and a confined cell.
  10. The device according to claim 1, wherein the plurality of resistive elements is arranged in a crossbar array, the crossbar array comprising a plurality of row lines, a plurality of column lines, and a plurality of junctions arranged between the plurality of row lines and the plurality of column lines, wherein each junction comprises a programmable resistive element and an access element for accessing the programmable resistive element.
  11. The device according to claim 1, wherein the device comprises a signal generator, the signal generator being configured to program the resistance of the plurality of resistive elements by an iterative program and verify procedure.
  12. A method for performing a short-term retention of data by a device (900) of any of claims 1 to 11, the method comprising: applying programming pulses to a subset of the plurality of resistive element to a set of second binary states with different retention periods (1001:1006) to provide temporary resistance changes of the subset from a respective first resistance state corresponding to a first binary state to a respective second resistance state corresponding to a second binary state, the respective temporary resistances of the resistive material of the subset changed for temporary predefined retention periods, wherein providing the resistance change comprises performing a temporary amorphization of the phase change material, thereby creating a set of amorphous volumes (1103a, 111a2, 1122a, 1132a). wherein respective resistances of the resistive material of the subset of the plurality of resistive elements reverts automatically after the respective predefined retention periods from the respective second resistance state to the respective first resistance state by a crystallization of the respective amorphous volumes, thereby automatically deleting the respective second binary states, wherein the device is configured to tune the respective predefined retention periods of the plurality of resistive elements by programming the subset of the plurality of resistive elements to a plurality of different amorphous volumes.

Description

BACKGROUND The present invention relates generally to the field of data security, and more particularly to a device with reconfigurable short term data retention. Data security/protection is the practice of protecting digital information from corruption, unauthorized access, or theft. The latter two are particularly becoming more and more relevant. For example, platforms such as social media not only provide users with the ability to auto-delete their posted (uploaded) data from the cloud, but also an option to define a time period to schedule the delete. In other applications, such as cache memories and encryption, data destruction is also needed to prevent hacking threats of important files, such as passwords. In modern systems, timer circuits and memory buffers are used for timed deletion of data. Modern computers use oscillator circuits to implement timers. These are usually large circuits. United States Patent Application publication number US 20081080226 A1, Mikolajick, T. et al. ("Memory system and method of operating the memory system", 2 April 2008) discloses a memory system including a plurality of resistive memory cell fields including at least a first resistive memory cell field and a second resistive memory cell field, the first resistive memory cell field formed with a plurality of resistive memory cells storing data at a first data storage speed, the second resistive memory cell field formed with a plurality of resistive memory cells storing data at a second data storage speed lower than the first data storage speed, and a controller controlling data transfer between the plurality of resistive memory cell fields. Qiu, K. et al. ("Write Mode Aware Loop Tiling for High Performance Low Power Volatile PCM in Embedded Systems", IEEE Transactions on Computers, IEEE, USA, vol. 65, no. 7, 1 July 2016, pages 2313 - 2324, XP011612877, ISSN: 0018-9340, discloses a write mode aware loop tiling approach for multi-level cell PCMs to effectively reduce the lifetime of write instances and maximize the number of efficient fast writes in loops. US2005/117387 A1 discloses a phase-change memory device including a phase-change memory cell having a volume of material which is programmable between amorphous and crystalline states. A write current source selectively applies a first write current pulse to program the phase-change memory cell into the amorphous state and a second write current pulse to program the phase-change memory cell into the crystalline state. US2009/201721 A1 discloses a phase change memory device and a write method thereof allowing writing of both volatile and non-volatile data on the phase change memory device. The phase change memory device may be written by setting a write mode as one of a volatile write mode and a non-volatile write mode, and writing data as volatile or non-volatile by applying a write pulse corresponding to the write mode. SUMMARY The present invention is defined by the appended claims. Embodiments of the invention will be described in more detail below, by way of illustrative and nonlimiting examples, with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS FIG. 1 is a simplified schematic block diagram of a device, according to an embodiment of the invention;FIG. 2 shows a memory crossbar array, according to an embodiment of the invention;FIG. 3 is a schematic illustration of the current/voltage characteristics of the material components of a phase change memory cell, according to an embodiment of the invention;FIG. 4A shows an exemplary resistive element according to an embodiment of the invention; FIG. 4B illustrates an embodiment for exploiting crystallization dynamics in a nanoscale device, in particular the phase change element shown in FIG. 4A, according to an embodiment of the invention;FIG. 5 illustrates in more detail the retention curves of resistive elements, according to embodiments of the invention, e.g., of the phase change elements as shown in FIG 4A;FIG. 6 illustrates the state dependent retention time of resistive elements, according to embodiments of the invention;FIG. 7 shows an application of a device comprising resistive elements, according to embodiments of the invention, in the area of data security;FIG. 8 shows an application of a device comprising resistive elements, according to embodiments of the invention, in the area of computational memories;FIG. 9 shows a memory crossbar array, according to embodiments of the invention;FIG. 10 shows a diagram showing exemplary retention curves of phase change elements comprising GeSb as phase change material, according to an embodiment of the invention;FIGS. 11A, 11B, 11C, and 11D show device geometries of resistive elements that may be used according to embodiments of the invention, wherein FIG. 11A shows a bridge cell, FIG. 11B shows a mushroom cell, FIG. 11C shows a trench cell, and FIG. 11D shows a confined cell;FIG. 12 shows a block diagram of an exemplary de