Search

EP-4550156-B1 - PREFETCH MEMORY MANAGEMENT UNIT FOR REAL-TIME VIRTUAL MEMORY ADDRESS TRANSLATION

EP4550156B1EP 4550156 B1EP4550156 B1EP 4550156B1EP-4550156-B1

Inventors

  • NEUMAN, DARREN
  • TUREAN, FLAVIU DORIN
  • MOMBERS, FRIEDERICH

Dates

Publication Date
20260513
Application Date
20240913

Claims (14)

  1. A method for real-time virtual memory address translation in an apparatus comprising system memory and a memory management unit (100) coupled to the system memory; wherein the memory management unit (100) comprises control logic (105), a first translation lookaside buffer (110), a second translation lookaside buffer (115), and a burst buffer (120); wherein the method comprises: fetching, by the first translation lookaside buffer (110), a first set of one or more first page table entries before a request to access data at a client address is received from a client, wherein the client address is an address in virtual memory space used by the client, and wherein the first set of one or more first page table entries is fetched based, at least in part, on a virtual address, wherein each first page table entry of the one or more first page table entries is associated with a respective page table address; storing, by the burst buffer (120), a plurality of second page table entries from a respective page table associated with a first page table address; fetching, by the second translation lookaside buffer (115), a first set of one or more second page table entries of the plurality of second page table entries from the burst buffer (120) based, at least in part, on the virtual address, and before the request to access data at the client address is received from the client; and transmitting, by the control logic (105), the virtual address to the first translation lookaside buffer (110) and to the second translation lookaside buffer (115), and causing the burst buffer (120) to store the plurality of second page table entries based, at least in part, on the virtual address.
  2. The method of claim 1, further comprising storing, by the burst buffer (120), a burst of table entries, wherein the plurality of second page table entries comprises sixteen page table entries.
  3. The method of claim 1 or 2, further comprising translating, by the first translation lookaside buffer (110), the virtual address to a first pointer physical address of the system memory, wherein the first set of one or more first page table entries are fetched by the first translation lookaside buffer (110) from the first pointer physical address.
  4. The method of any one of the claims 1 to 3, further comprising generating, by the second translation lookaside buffer (115), a virtual address tag based, at least in part, on the virtual address, wherein the virtual address tag is associated with the first set of one or more second page table entries; and receiving, by the second translation lookaside buffer (115), the client address, and comparing the virtual address tag with a first portion of the client address.
  5. The method of claim 4, further comprising, in response to determining that the virtual address tag and the first portion of the client address match, selecting, by the second translation lookaside buffer (115), a respective second page table entry of the one or more second page table entries stored at the second translation lookaside buffer (115) based, at least in part, on a second portion of the client address different from the first portion.
  6. The method of claim 5, wherein the apparatus further comprises address remapping logic (130), and the method further comprising remapping, by the address remapping logic (130), the client address to a physical address of the system memory based, at least in part, on the respective second page table entry selected by the second translation lookaside buffer (115).
  7. The method of claim 5 or 6, further comprising, in response to determining that the virtual address tag and the first portion of the client address do not match, fetching, by the second translation lookaside buffer (115), a second set of one or more second page table entries from the burst buffer (120), wherein the second set of one or more second page table entries is different from the first.
  8. The method of claim 7, further comprising, in response to determining that the virtual address tag and the first portion of the client address do not match, determining, by the control logic (105), whether the first set of one or more first page table entries stored in the first translation lookaside buffer (110) is associated with the client address.
  9. The method of claim 8, further comprising, in response to determining that none of the first set of one or more first page table entries are associated with the client address, generating, by the first translation lookaside buffer (110), a second pointer physical address of the system memory based, at least in part, on the client address, and fetching a second set of one or more first page table entries based on the second pointer physical address.
  10. The method of any one of the claims 1 to 9, further comprising: transmitting the virtual address to the first translation lookaside buffer (110) and to a second translation lookaside buffer (115); storing, by the first translation lookaside buffer (110), the first set of one or more first page table entries; storing, by the burst buffer (120), a plurality of second page table entries based, at least in part, on the virtual address; and storing, by the second translation lookaside buffer (115), the first set of one or more second page table entries.
  11. A memory management unit (100) comprising control logic (105), a first translation lookaside buffer (110), a second translation lookaside buffer (115), and a burst buffer (120); wherein the memory management unit (100) is configured to carry out the method of any one of the claims 1 to 10.
  12. An apparatus comprising system memory and the memory management unit (100) of claim 11 coupled to the system memory.
  13. A non-transitory computer-readable storage medium comprising a set of instructions that, when executed by one or more processors, cause the processors to carry out the method of any one of the claims 1 to 10.
  14. A system comprising system memory, a processor coupled to the system memory, and a non-transitory computer readable storage medium of claim 13.

Description

FIELD The present disclosure relates, in general, to methods, systems, and apparatuses for real-time virtual memory address translation in memory management units. BACKGROUND Conventionally, real-time hardware access of dynamic random-access memory (DRAM) is controlled by a strict schedule. Meanwhile, virtual memory management is useful for application processors and Linux. Using virtual memory for hardware involves additional memory access steps to read virtual memory page tables, followed by memory access for video clients. Combining the use of virtual memory with the rigid deadlines for fetching data stored in memory often results in real-time applications (such as video processing) missing hard real-time deadlines. Thus, a memory management unit (MMU) with prefetch functionality for real-time virtual address translation is provided. US 2022/309001 A1 discloses a method for performing cache prefetching process in computer processing system, involves performing translation lookaside buffer lookup in TLB based on one of demand access stream or prefetch request. BRIEF DESCRIPTION OF THE DRAWINGS A further understanding of the nature and advantages of particular embodiments may be realized by reference to the remaining portions of the specification and the drawings, in which like reference numerals are used to refer to similar components. In some instances, a sub-label is associated with a reference numeral to denote one of multiple similar components. When reference is made to a reference numeral without specification to an existing sub-label, it is intended to refer to all such multiple similar components. Fig. 1 is a schematic block diagram of an architecture for a virtual memory prefetch MMU, in accordance with various embodiments;Fig. 2 is a schematic block diagram of a L2 TLB for a prefetch MMU, in accordance with various embodiments;Fig. 3 is a schematic diagram of an L1 TLB for prefetch, in accordance with various embodiments; andFig. 4 is a schematic diagram of prefetch FIFO control logic, in accordance with various embodiments. DETAILED DESCRIPTION OF EMBODIMENTS The invention is defined in the appended claims. The dependent claims set out particular embodiments. Various embodiments set forth a framework and implementation for real-time virtual memory address translation utilizing a prefetch MMU. In some embodiments, an apparatus for a prefetch MMU is provided. The apparatus includes system memory, and a memory management unit coupled to the system memory. The memory management unit includes a first translation lookaside buffer, burst buffer, second translation lookaside buffer and control logic. The first translation lookaside buffer is configured to fetch a first set of one or more first page table entries before a request to access data at a client address is received from a client, wherein the client address is an address in virtual memory space used by the client, and wherein the first set of one or more first page table entries is fetched based, at least in part, on a virtual address. The burst buffer stores a plurality of second page table entries from a respective page table associated with a first page table address. A second translation lookaside buffer is configured to fetch a first set of one or more second page table entries of the plurality of second page table entries from the burst buffer based, at least in part, on the virtual address, and before the request to access data at the client address is received from the client. The control logic is configured to transmit the virtual address to the first and second translation lookaside buffers, and cause the burst buffer to store the plurality of second page table entries. In further embodiments, a prefetch MMU is provided. The prefetch MMU includes a first translation lookaside buffer, burst buffer, second translation lookaside buffer and control logic. The first translation lookaside buffer is configured to prefetch a first set of one or more first page table entries based, at least in part, on a virtual address, and wherein the prefetch of the first set of one or more first page table entries occurs before a request to access data at a client address is received from a client, wherein the client address is an address in virtual memory space used by the client. The burst buffer stores a plurality of second page table entries from a respective page table associated with a first page table address. A second translation lookaside buffer is configured to prefetch a first set of one or more second page table entries of the plurality of second page table entries from the burst buffer based, at least in part, on the virtual address, wherein the prefetch of the first set of one or more second page table entries occurs before a request to access data at a client address is received from the client. The control logic is configured to transmit the virtual address to the first and second translation lookaside buffers, and cause the burst buffer t