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EP-4554356-B1 - METHOD FOR MANUFACTURING A QUANTUM ELECTRONIC CIRCUIT WITH REDUCED GATE PITCH

EP4554356B1EP 4554356 B1EP4554356 B1EP 4554356B1EP-4554356-B1

Inventors

  • NIEBOJEWSKI, HEIMANU

Dates

Publication Date
20260513
Application Date
20241105

Claims (11)

  1. A method for manufacturing an electronic circuit (1) comprising quantum dots from a substrate (4), comprising the steps of: - forming, on the substrate, first gate electrodes (51) spaced apart from each other, each first gate electrode (51) having a first branch (51a) extending in parallel to a first direction (X), the first branches (51a) of the first gate electrodes (51) being distributed at a constant pitch R, measured along a second direction (Y) perpendicular to the first direction (X); - forming spacers (71) against the first gate electrodes (51); - forming, on the substrate (4), second gate electrodes (52), each second gate electrode (52) being disposed between two neighbouring first gate electrodes (51) and separated from each of them (51) by one of the spacers (71), each second gate electrode (52) having a first branch (52a) extending between the two first branches (51a) of the neighbouring first gate electrodes (51); and - forming, as a replacement of the spacers (71), third gate electrodes (53), each third gate electrode (53) being disposed between a first gate electrode (51) and second gate electrode (52) which are neighbouring, each third gate electrode (52) having a first branch (53a) extending between a first branch (51a) of a first gate electrode (51) and a first branch (52a) of a second gate electrode (52); wherein the first, second, and third gate electrodes (51, 52, 53) extend at least partially over a portion (2) of the substrate (4), known as the "active area," configured to accommodate the quantum dots.
  2. The manufacturing method according to the preceding claim, wherein replacing the spacers (71) by the third gate electrodes (53) comprises selectively etching the spacers with respect to the first and second gate electrodes (51, 52).
  3. The manufacturing method according to one of the preceding claims, wherein: - the first gate electrodes (51) are formed from a first sacrificial material, such as polycrystalline silicon; - the second gate electrodes (52) are formed from a second conductive material, such as titanium nitride; and - the method comprises a step of replacing the first sacrificial material of the first gate electrodes (51) with the second conductive material.
  4. The manufacturing method according to one of the preceding claims, wherein: - each first gate electrode (51) is formed so that the first branch (51a) has a first width (W51a), measured along the second direction (Y), less than or equal to R/4; and - the spacers (71) are formed so as to have a second width (W71), measured along the second direction (Y) and at the first branches (51a) of the first gate electrodes (51), less than or equal to R/4.
  5. The manufacturing method according to one of the preceding claims, wherein each third gate electrode (53) is formed so as to extend between neighbouring first and second gate electrodes (51, 52) and so as to have at least one so-called "free portion", extending beyond said neighbouring first and second gate electrodes.
  6. The manufacturing method according to the preceding claim, comprising, after forming the spacers (71) and prior to forming the second gate electrodes (52), partially etching each first gate electrode (51) from one end (515, 516), etching being carried out selectively with respect to the spacers (71) so that each spacer has a free portion (711, 712) extending beyond the first gate electrodes (51), forming the second gate electrodes (52) being such that said spacer portions (711, 712) also extend beyond the second gate electrodes (51) and so that when the third gate electrodes are formed (53), each third gate electrode (53) has, after replacing each spacer (71), a free portion (53c, 53d) extending beyond the first and second gate electrodes (51, 52).
  7. The manufacturing method according to one of the two preceding claims, comprising, after forming the third gate electrodes (53), a step of reconnecting to each free portion (53c, 53d) of the third gate electrodes (53) extending beyond the first and second gate electrodes (51, 52).
  8. The manufacturing method according to one of the preceding claims, wherein, forming the first gate electrodes (51) is carried out so that each of the first, second and third gate electrodes (51) also comprises a second branch (51b, 52b, 53b) extending perpendicularly to its first branch (51a, 52a, 53a).
  9. The manufacturing method according to the preceding claim, wherein forming the second branches (51b, 52b) of the first and second gate electrodes (51, 52) is carried out so that, for each of the first and second gate electrodes (51, 52), a width of the second branch (51b, 52b), measured along the first direction (X), is strictly greater than a width of the first branch (51a, 52a).
  10. The manufacturing method according to one of the two preceding claims, comprising reconnecting to the second branch (51b, 52b) of each first gate electrode (51) and of each second gate electrode (52).
  11. The manufacturing method according to one of claims 1 to 8, comprising, prior to forming each second gate electrode (52) and/or of each third gate electrode (53), depositing a dielectric layer, referred to as "gate oxide", onto the substrate (4) between two neighbouring first gate electrodes (51), the forming of each second gate electrode (52) and/or of each third gate electrode (53) being carried out on the gate oxide.

Description

TECHNICAL FIELD OF THE INVENTION The technical field of the invention is that of quantum electronics and more particularly the manufacture of such a circuit. TECHNOLOGICAL BACKGROUND OF THE INVENTION The manipulation of quantum states, also called "qubits" (short for "quantum bits"), offers new possibilities in information manipulation. There are several types of qubits, such as spin qubits, for which information is stored in the quantum state of a spin. Quantum electronic circuits capable of manipulating spin qubits include islands, also called quantum dots, which can store qubits for the duration of their manipulation and measurement. There Fig. 1 This represents a simplified example of a commonly implemented AA1 electronic circuit architecture. According to this architecture, AA21 quantum dots are formed within a semiconducting layer AA11, known as the qubit layer. The AA21 dots correspond to wells formed in the electrostatic potential AA20 of the AA11 qubit layer by means of conductive electrodes AA13, called "gate electrodes" or "gates." The AA13 gates are arranged on the AA11 qubit layer and electrically isolated from it by a dielectric layer AA12, called "gate oxide" because it is frequently formed by an oxide. Modulating the electrical potential of the AA13 gates allows the shape of the AA21 quantum dots to be modulated. When each AA21 dot contains an A2 qubit, these modulations allow the manipulation of the AA2 qubits. The integration of AA21 quantum dots into electronic circuits must meet several requirements. Firstly, it must offer high integration density to provide significant computing power. Secondly, the fabrication processes for these quantum electronic circuits must ensure low circuit variability. Indeed, the efficiency of storing and manipulating AA2 qubits is heavily dependent on the position of the qubits within the AA21 quantum dots. However, these can be influenced by their environment. There Fig. 2 considers the circuit of the Fig. 1 in which an AA14 charge distribution is dispersed within the AA11 qubit layer and/or the AA12 dielectric layer. These AA14 charges correspond, for example, to dopants or diluted vacancies within these AA11 and AA12 layers. This AA14 charge distribution modifies the AA20 electrostatic potential at the AA11 qubit layer and distorts the AA21 quantum dots. Parasitic AA21' potential wells can form, trapping the AA2 qubits. The AA2 qubits thus become erratically located instead of being aligned with the AA13 grids. Manipulating the AA2 qubits becomes more difficult. To reduce the impact of AA14 electrical charges on the localization of qubits 2, it is known to reduce the spacing between neighboring AA13 grids. Reducing the spacing between these AA13 grids is equivalent to reducing the distribution interval between these AA13 grids, called the pitch. A grid pitch of less than 80 nm, and preferably less than 25 nm, effectively counteracts the impact of the AA14 electrical charge distribution on the AA21 boxes. However, fabricating an electronic circuit with a significantly reduced grid pitch raises new challenges. The fabrication of AA13 grids with a pitch smaller than 25 nm, for example, requires the implementation of extreme ultraviolet (EUV) lithography steps. This type of lithography requires expensive and complex equipment. Furthermore, it can lead to pitch walking when several EUV lithography steps are performed consecutively. A small grid pitch also complicates the alignment of electrical contacts on each grid. Misalignment or contact overflow can short-circuit multiple grids, rendering the circuit unusable. The document US 2019/0140073 A1 describes a process for fabricating a quantum device from a substrate onto which initial grids are laid. These initial grids are arranged parallel to each other and according to an initial grid pitch. Secondary grids are formed between the initial grids. The first and second grids are thus distributed with a reduced pitch, equal to half the initial grid pitch. This process reduces the final grid pitch of the quantum circuit. However, unless EUV lithography steps are implemented, it does not allow for a final pitch small enough to improve qubit localization. The document WO 2023/117063 A1 discloses a quantum device comprising a plurality of grid electrodes distributed at a regular pitch. The document US 2022/231132 A1 discloses a manufacturing process for a quantum device comprising, among other things, the following steps: forming, on the substrate, first gate electrodes; forming spacers between said first gate electrodes; forming, in replacement of said spacers, second gate electrodes. The document EP 4 030 487 A1 discloses a method for manufacturing a quantum device in which, firstly, first grid electrodes are formed on a substrate; spacers are then formed against the first electrodes; and second grid electrodes are formed between two adjacent first grid electrodes, each separated by a spacer. Quantum devices are al