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EP-4555417-B1 - LATENCY AND POWER EFFICIENT CLOCK AND DATA RECOVERY IN A HIGH-SPEED ONE-WIRE BIDIRECTIONAL BUS

EP4555417B1EP 4555417 B1EP4555417 B1EP 4555417B1EP-4555417-B1

Inventors

  • MISHRA, Lalan Jee
  • SRIKANTIAH, UMESH
  • GATTA, FRANCESCO
  • OZEL, MUHLIS KENAN
  • WIETFELDT, RICHARD DOMINIC

Dates

Publication Date
20260506
Application Date
20230530

Claims (15)

  1. A clock and data recovery apparatus (1500, 1700), comprising: an oscillator (1510, 1710) configured to generate a base clock signal with a base frequency; a clock gating circuit (1506, 1706) responsive to one or more control inputs and configured to output a gated base clock signal while the clock gating circuit (1506, 1706) is enabled; a first counter (1512, 1712) clocked by the gated base clock signal and configured to provide a counter output that reflects a count of positive and negative edges in the gated base clock signal; control logic (1516, 1716) coupled to a first control input of the clock gating circuit (1506, 1706) and configured to disable the clock gating circuit (1506, 1706) when the counter output corresponds to a maximum count value; and an edge synchronization circuit (1508, 1702) coupled to a one-wire bus and configured to: ignore edges in a signal received from the one-wire bus while the counter output has a value that is less than the maximum count value; and reset the first counter (1512, 1712) in response to an edge detected in the signal received from the one-wire bus.
  2. The clock and data recovery apparatus (1500, 1700) of claim 1, wherein the signal received from the one-wire bus is Manchester-encoded based on an encoding clock having a frequency that is four times greater than the base frequency of the base clock signal, wherein preferably the encoding clock has a frequency of at least 52 MHz.
  3. The clock and data recovery apparatus (1500, 1700) of claim 1, further comprising: a flipflop configured to capture a data bit from the one-wire bus in response to an edge detected in the signal received from the one-wire bus.
  4. The clock and data recovery apparatus (1500, 1700) of claim 3, wherein a signal output by the control logic that disables the clock gating circuit is used to clock the flipflop.
  5. The clock and data recovery apparatus of claim 1, wherein a signal output by the control logic (1516, 1716) that disables the clock gating circuit (1506, 1706) is used to generate a write clock signal that is output by the clock and data recovery apparatus (1500, 1700).
  6. The clock and data recovery apparatus (1500, 1700) of claim 1, further comprising: a second counter (1504, 1704) clocked by the signal received from the one-wire bus and configured to drive a second control input of the clock gating circuit (1506, 1706), wherein the second counter (1504, 1704) is held in a reset state when the one-wire bus is idle and until a sequence start condition, SSC, is detected in the signal received from the one-wire bus, wherein the second counter (1504, 1704) is configured to halt counting when an expected number of synchronization pulses have been counted in the signal received from the one-wire bus, and wherein the clock gating circuit (1506, 1706) is disabled until the second counter (1504, 1704) halts counting, wherein the second counter (1504, 1704) is reset when an output by the control logic (1516, 1716) that disables the clock gating circuit (1506, 1706) is used to generate a write clock signal that is output by the clock and data recovery apparatus (1500, 1700).
  7. The clock and data recovery apparatus (1500, 1700) of claim 1, wherein the signal received from the one-wire bus carries a datagram configured in accordance with a Radio Frequency Front-End, RFFE, protocol and encoded using Manchester encoding.
  8. A method (2200) of data communication, comprising: configuring (2202) an oscillator to generate a base clock signal with a base frequency; configuring (2204) a clock gating circuit to output a gated base clock signal while the clock gating circuit is enabled, the clock gating circuit being responsive to one or more control inputs; configuring (2206) a first counter to provide a counter output that reflects a count of positive and negative edges in the gated base clock signal that clocks the first counter; configuring (2208) control logic to disable the clock gating circuit when the counter output corresponds to a maximum count value; and configuring (2210) an edge synchronization circuit to: ignore edges in a signal received by the edge synchronization circuit from a one-wire bus while the counter output has a value that is less than the maximum count value; and reset the first counter in response to an edge detected in the signal received from the one-wire bus.
  9. The method (2200) of claim 8, wherein the signal received from the one-wire bus is Manchester-encoded based on an encoding clock having a frequency that is four times greater than the base frequency of the base clock signal, wherein preferably the encoding clock has a frequency of at least 52 MHz.
  10. The method (2200) of claim 8, further comprising: configuring a flipflop to capture a data bit from the one-wire bus in response to an edge detected in the signal received from the one-wire bus.
  11. The method (2200) of claim 10, wherein a signal output by the control logic that disables the clock gating circuit is used to clock the flipflop.
  12. The method (2200) of claim 8, further comprising: generating an output signal using a signal output by the control logic that disables the clock gating circuit, the output signal being configured to provide timing for writing data captured from the one-wire bus.
  13. The method (2200) of claim 8, further comprising: configuring a second counter to drive a control input of the clock gating circuit, the second counter being clocked by the signal received from the one-wire bus, wherein the second counter is held in a reset state when the one-wire bus is idle and until a sequence start condition, SSC, is detected in the signal received from the one-wire bus, wherein the second counter is configured to halt counting when an expected number of synchronization pulses have been counted in the signal received from the one-wire bus, and wherein the clock gating circuit is disabled until the second counter halts counting, wherein the second counter is reset when an output by the control logic that disables the clock gating circuit is used to generate an output signal configured to provide timing for writing data captured from the one-wire bus.
  14. The method (2200) of claim 8, wherein the signal received from the one-wire bus carries a datagram configured in accordance with a Radio Frequency Front-End, RFFE, protocol and encoded using Manchester encoding.
  15. A processor-readable storage medium (2106) storing code thereon, the code when executed by a processor (2104) in a processing circuit (2102) causes the processing circuit (2102) to: configure an oscillator to generate a base clock signal with a base frequency; configure a clock gating circuit to output a gated base clock signal while the clock gating circuit is enabled, the clock gating circuit being responsive to one or more control inputs; configure a first counter to provide a counter output that reflects a count of positive and negative edges in the gated base clock signal that clocks the first counter; configure control logic to disable the clock gating circuit when the counter output corresponds to a maximum count value; and configure an edge synchronization circuit to: ignore edges in a signal received by the edge synchronization circuit from a one-wire bus while the counter output has a value that is less than the maximum count value; and reset the first counter in response to an edge detected in the signal received from the one-wire bus.

Description

TECHNICAL FIELD The present disclosure relates generally to serial communication and, more particularly, to clock generation at receivers coupled to a one-wire communication bus. BACKGROUND Mobile communication devices may include a variety of components including circuit boards, integrated circuit (IC) devices and/or System-on-Chip (SoC) devices. The components may include processing circuits, user interface components, storage and other peripheral components that communicate through a serial bus. The serial bus may be operated in accordance with a standardized or proprietary protocol. In one example, a serial bus is operated in accordance with an Inter-Integrated Circuit (I2C bus or I2C) protocol. The I2C bus was developed to connect low-speed peripherals to a processor, where the I2C bus is configured as a multi-drop bus. A two-wire I2C bus includes a Serial Data Line (SDA) that carries a data signal, and a Serial Clock Line (SCL) that carries a clock signal. In another example, the Improved Inter-Integrated Circuit (I3C) protocols defined by the Mobile Industry Processor Interface (MIPI) Alliance derive certain implementation aspects from the I2C protocol including separate clock and data lines. In another example, the Radio Frequency Front-End (RFFE) interface defined by the MIPI Alliance provides a communication interface for controlling various radio frequency (RF) front-end devices, including power amplifiers (PAs), low-noise amplifiers (LNAs), antenna tuners, filters, sensors, power management devices, switches, etc. These devices may be collocated in a single IC device or provided in multiple IC devices. In another example, the system power management interface (SPMI) defined by the MIPI Alliance provides a hardware interface that may be implemented between baseband or application processors and peripheral components. In some implementations, the SPMI is deployed to support power management operations within a device. The use of MIPI-defined serial buses in place of parallel buses can reduce the number of physical general-purpose input/output (GPIO) pins required to support communication between multiple devices. However, as device complexity increases, demand for GPIO pins also increases and there is demand for more simplified bus architectures, including bus architectures that support communication through a single GPIO pin and over a single wire. US 2005/175133 A1 is disclosing a clock synchronisation circuit for a single-wire bus. SUMMARY The present invention is defined by the appended independent claims. Further embodiments of the present invention are defined by the appended dependent claims. Certain aspects of the disclosure relate to systems, apparatus, methods and techniques that enable clock generation at a receiving device sufficient to support communication over a single-wire serial bus. Clock signals generated at the receiver are synchronized to every transition in a Manchester-encoded signal that encodes a data bit. In some examples, transmitter clock signal used to generate the Manchester-encoded signal is reconstructed and can serve as a replacement for a clock signal that would have been transmitted over a two-wire serial bus. Phase and frequency errors can be accommodated and accumulation of such errors is prevented. The single-wire link may format datagrams in accordance with RFFE, SPMI or another standards-defined protocol. In various aspects of the disclosure, a clock and data recovery apparatus includes an oscillator configured to generate a base clock signal with a base frequency, a clock gating circuit responsive to one or more control inputs and configured to output a gated base clock signal while the clock gating circuit is enabled, a first counter clocked by the gated base clock signal and configured to provide a counter output that reflects a count of positive and negative edges in the gated base clock signal, control logic coupled to a first control input of the clock gating circuit and configured to disable the clock gating circuit when the counter output corresponds to a maximum count value, and an edge synchronization circuit coupled to a one-wire bus. The edge synchronization circuit is configured to ignore edges in a signal received from the one-wire bus while the counter output has a value that is less than the maximum count value, and reset the first counter in response to an edge detected in the signal received from the one-wire bus. In various aspects of the disclosure, a method of data communication includes configuring an oscillator to generate a base clock signal with a base frequency, configuring a clock gating circuit to output a gated base clock signal while the clock gating circuit is enabled, the clock gating circuit being responsive to one or more control inputs, configuring a first counter to provide a counter output that reflects a count of positive and negative edges in the gated base clock signal that clocks the first counter, configuring control