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EP-4557098-B1 - COMPUTING DEVICE WITH INDEPENDENTLY COHERENT NODES

EP4557098B1EP 4557098 B1EP4557098 B1EP 4557098B1EP-4557098-B1

Inventors

  • TAVALLAEI, SIAMAK
  • AGARWAL, Ishwar

Dates

Publication Date
20260513
Application Date
20210601

Claims (12)

  1. A method (500) for memory address mapping, comprising: at a central IO die communicatively connected to two or more independently coherent compute nodes, receiving (510) a memory access request from a first compute node including a host physical address for the first compute node; mapping (520) the host physical address for the received request to a system address map including ranges of host physical addresses for each of the two or more independently coherent compute nodes; outputting (530) a package physical address based on the mapped host physical address; mapping (540) the package physical address to a physical element of a memory unit selectively coupled to the first compute node via the central IO die; and providing (550) the first compute node access to the physical element of the memory unit by using the package physical address.
  2. The method of claim 1, wherein the system address map includes contiguous address slabs of equal length for each of the two or more nodes.
  3. The method of claim 1, wherein the package physical address includes a node ID appended to the host physical address.
  4. The method of claim 1, wherein a range of the host physical addresses is interleaved among available home agents and memory channels included in the central IO die.
  5. A computer-readable medium having stored computer-executable instructions that, when executed by a computer, cause the computer to perform a method (500) for memory address mapping, the method comprising: at a central IO die communicatively connected to two or more independently coherent compute nodes, receiving (510) a memory access request from a first compute node including a host physical address for the first compute node; mapping (520) the host physical address for the received request to a system address map including ranges of host physical addresses for each of the two or more independently coherent compute nodes; outputting (530) a package physical address based on the mapped host physical address; mapping (540) the package physical address to a physical element of a memory unit selectively coupled to the first compute node via the central IO die; and providing (550) the first compute node access to the physical element of the memory unit by using the package physical address.
  6. The computer-readable medium, wherein the system address map includes contiguous address slabs of equal length for each of the two or more nodes.
  7. The computer-readable medium of claim 5, wherein the package physical address includes a node ID appended to the host physical address.
  8. The computer-readable medium of claim 5, wherein a range of the host physical addresses is interleaved among available home agents and memory channels included in the central IO die.
  9. A computer device adapted to perform a method (500) for memory address mapping, the method comprising: at a central IO die communicatively connected to two or more independently coherent compute nodes, receiving (510) a memory access request from a first compute node including a host physical address for the first compute node; mapping (520) the host physical address for the received request to a system address map including ranges of host physical addresses for each of the two or more independently coherent compute nodes; outputting (530) a package physical address based on the mapped host physical address; mapping (540) the package physical address to a physical element of a memory unit selectively coupled to the first compute node via the central IO die; and providing (550) the first compute node access to the physical element of the memory unit by using the package physical address.
  10. The computer device of claim 9, wherein the system address map includes contiguous address slabs of equal length for each of the two or more nodes.
  11. The computer device of claim 9, wherein the package physical address includes a node ID appended to the host physical address.
  12. The computer device of claim 9, wherein a range of the host physical addresses is interleaved among available home agents and memory channels included in the central IO die.

Description

BACKGROUND Data centers typically include large numbers of discrete compute nodes, such as server computers or other suitable computing devices. Such devices may work independently and/or cooperatively to fulfill various computational workloads. Sets of compute nodes may be brought together into a single package in order to share resources and reduce inter-node distances. US 10 445 229 B1 provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. The host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to "plan ahead" in a manner supporting host issuance of true multi-plane read commands. SUMMARY It is the object of the present invention to improve prior art systems. This object is solved by the subject matter of the independent claims. Preferred embodiments are defined by the dependent claims. This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. Furthermore, the claimed subject matter is not limited to implementations that solve any or all disadvantages noted in any part of this disclosure. A computing device comprises two or more compute nodes, that each include two or more processor cores. Each compute node comprises an independently coherent domain that is not coherent with other compute nodes. A central IO die is communicatively coupled to each of the two or more compute nodes. A plurality of natively-attached volatile memory units are attached to the central IO die via one or more memory controllers. The central IO die includes one or more home agents for each compute node. The home agents are configured to map memory access requests received from the compute nodes to one or more addresses within the natively-attached volatile memory units. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 schematically depicts a plurality of compute nodes communicatively coupled with a disaggregated memory pool.FIG. 2 schematically shows an example multi-node system-on-a-chip with a central IO die.FIG. 3 schematically shows one example compute node of the system of FIG. 2.FIG. 4 schematically shows an example cache organization schema for an example compute node.FIG. 5 is an example method for memory address mapping across multiple compute nodes.FIG. 6 schematically shows an example data structure for mapping memory addresses across multiple compute nodes.FIG. 7 schematically shows an example architecture for an IO die of the system of FIG. 2.FIG. 8 schematically shows an example coherence map for a computing system.FIG. 9A schematically shows a traditional system accessing IO devices across multiple compute nodes.FIG. 9B schematically shows a system for pooling IO devices across multiple compute nodes according to the present disclosure.FIG. 10 schematically shows an example computing system. DETAILED DESCRIPTION As discussed above, data centers typically include large numbers of discrete compute nodes, such as server computers or other suitable computing devices. Such compute nodes may be referred to as "host computing devices," or "hosts," as they may in some cases be used to host a plurality of virtual machines. It will be understood, however, that a compute node may be used for any suitable computing purpose, and need not be used for hosting virtual machines specifically. Furthermore, in some examples, a compute node may be implemented as a virtual machine. Depending on the specific implementation, each individual compute node may have any suitable collection of computer hardware. Regardless, each individual compute node will typically include some local collection of hardware resources, including data storage, memory, processing resources, etc. However, computational workloads (e.g., associated with data center customers) are often not uniformly distributed between each of the compute nodes in the data center. Rather, in a common scenario, a subset of compute nodes in the data center may be tasked with resource-intensive workloads, while other compute nodes sit idle or handle relatively less resource-intensive tasks. Thus, the total resource utilization of the data cent