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EP-4557906-B1 - METHOD FOR READING THREE-DIMENSIONAL FLASH MEMORY

EP4557906B1EP 4557906 B1EP4557906 B1EP 4557906B1EP-4557906-B1

Inventors

  • CHEN, ZILONG
  • FU, Xiang

Dates

Publication Date
20260513
Application Date
20191023

Claims (12)

  1. A method for operating a target memory cell in a three-dimensional (3D) memory device comprising memory strings, the method comprising a program operation and a verification operation, and wherein the verification operation comprises: applying, on an unselected top select gate (Unsel_TSG) of an unselected memory string, a prepare voltage (Vprepare) at a first time period of a prepare step and a first off voltage (Voff) at a second time period of a sensing step, wherein the prepare voltage is larger than a threshold voltage of the unselected top select gate (Unsel_TSG); applying, at a time point of the prepare step, a top select gate voltage (Vtsg) and a lower select gate voltage (Vlsg) on a selected top select gate (Sel_TSG) and a lower select gate (LSG) of a selected memory string respectively, wherein applying a top select gate voltage (Vtsg) on a selected top select gate (Sel_TSG) of a selected memory string comprises applying the top select gate voltage (Vtsg) for electrically connecting the selected memory string to a bit line; and applying a lower select gate voltage (Vlsg) comprises applying the lower select gate voltage (Vlsg) for electrically connecting the selected memory string to an array common source; applying, on a selected word line (Sel_WL) associated with the target memory cell, a second off voltage during the first time period of the prepare step and a read voltage (Vread) during the second time period of the sensing step; and applying, on an unselected word line (Unsel_WL), a pass voltage (Vpass) during the first time period of the prepare step and during the second time period of the sensing step, wherein the prepare step is prior to the sensing step and applying the prepare voltage (Vprepare) on the unselected top select gate (Unsel TSG) is prior to applying the pass voltage (Vpass) on the unselected word line (Unsel WL).
  2. The method of claim 1, further comprising: ramping up the prepare voltage(Vprepare) on the unselected top select gate (Unsel TSG) before ramping up the pass voltage on the unselected word line(Unsel WL).
  3. The method of claim 1, wherein the unselected word line (Unsel WL) reaches the pass voltage after the unselected top select gate (Unsel TSG) at the prepare voltage(Vprepare).
  4. The method of claim 1, further comprising ramping up the top select gate voltage (Vtsg) on the selected top select gate (Sel_TSG) and the lower select gate voltage(Vlsg) on the lower select gate (LSG) before ramping up the pass voltage on the unselected word line(Unsel WL).
  5. The method of claim 4, wherein the unselected word line (Unsel WL) reaches the pass voltage after the selected top select gate (Sel TSG) at the selected top select gate voltage (Vtsg) and the lower select gate (LSG) at the lower select gate voltage (Vlsg).
  6. The method of claim 1, wherein applying the first off voltage on the unselected top select gate (Unsel_TSG) during the second time period to switch off the unselected top select transistor (Unsel_TSG).
  7. The method of claim 6, wherein applying the read voltage on the selected word line (Sel_WL) before the unselected top select transistor is switched off.
  8. A three-dimensional (3D) memory device (100), comprising: a memory array (300), comprising a plurality of memory strings (212) extending vertically through a stack (335) of alternating conductive and dielectric layers, wherein each memory string (212) comprises a plurality of memory cells (340-1, 340-2, 340-3); and a peripheral circuit coupled to the memory array (300) and configured to perform, on a target memory cell (340-3) of the memory array (300), a program operation and a verification operation, and the verification operation including a sensing step and a read-prepare step prior to the sensing step, wherein the verification operation comprises: applying, on an unselected top select gate (Unsel_TSG) of an unselected memory string, a prepare voltage (Vprepare) during a first time period of a prepare step and a first off voltage (Voff) during a second time period of a sensing step, wherein the prepare voltage is larger than a threshold voltage of the unselected top select gate (Unsel_TSG); applying, at a time point of the prepare step, a top select gate voltage (Vtsg) and a lower select gate voltage (Vlsg) on a selected top select gate (Sel_TSG) and a lower select gate (LSG) of a selected memory string respectively; wherein applying a top select gate voltage (Vtsg) on a selected top select gate (Sel_TSG) of a selected memory string comprises applying the top select gate voltage (Vtsg) for electrically connecting the selected memory string to a bit line; and applying a lower select gate voltage (Vlsg) comprises applying the lower select gate voltage (Vlsg) for electrically connecting the selected memory string to an array common source; applying, on a selected word line (Sel_WL) associated with the target memory cell, a second off voltage during the first time period of the prepare step and a read voltage (Vread) during the second time period of the sensing step; and applying, on an unselected word line (Unsel_WL), a pass voltage (Vpass) during the first time period of the prepare step and during the second time period of the sensing step; wherein the prepare step is prior to the sensing step and applying the prepare voltage (Vprepare) on the unselected top select gate (Unsel TSG) is prior to applying the pass voltage (Vpass) on the unselected word line (Unsel WL).
  9. The three-dimensional (3D) memory device (100) of claim 8, wherein the verification operation further comprises ramping up the prepare voltage(Vprepare) on the unselected top select gate (Unsel TSG) before ramping up the pass voltage on the unselected word line(Unsel WL).
  10. The three-dimensional (3D) memory device (100) of claim 8, wherein the unselected word line (Unsel WL) reaches the pass voltage after the unselected top select gate (Unsel TSG) at the prepare voltage(Vprepare).
  11. The three-dimensional (3D) memory device (100) of claim 8, wherein the verification operation further comprises ramping up the top select gate voltage (Vtsg) on the selected top select gate (Sel_TSG) and the lower select gate voltage(Vlsg) on the lower select gate (LSG) before ramping up the pass voltage on the unselected word line (Unsel WL).
  12. The three-dimensional (3D) memory device (100) of claim 11, wherein the unselected word line (Unsel WL) reaches the pass voltage after the selected top select gate (Sel TSG) at the selected top select gate voltage (Vtsg) and the lower select gate (LSG) at the lower select gate voltage (Vlsg).

Description

TECHNICAL FIELD The present disclosure generally relates to the field of semiconductor technology, and more particularly, to a method for reading a three-dimensional (3D) memory. BACKGROUND As memory devices are shrinking to smaller die size to reduce manufacturing cost and increase storage density, scaling of planar memory cells faces challenges due to process technology limitations and reliability issues. A three-dimensional (3D) memory architecture can address the density and performance limitation in planar memory cells. In a 3D NAND flash memory, memory cells can be programmed for data storage based on charge-trapping technology. The storage information of a memory cell depends on the amount of charge trapped in a storage layer. However, fast charges, i.e., charges trapped in shallow traps, can be easily lost. Therefore, the threshold voltage determining the stored information can be different between write and read operations. Accordingly, a read-prepare step is included in a read-verification operation after programming to remove the fast charges and verify the threshold voltage of the memory cell. Fast charge loss depending on the intrinsic de-trapping process in the storage layer can be long, making the read-verification operation inefficient. Therefore, a need exists for a method to accelerate fast charge loss so that threshold voltage or storage information of the memory cell can be verified or read more accurately and efficiently. US 2015/036426 A1 and US 2018/137925 A1 disclose methods of operation of NAND flash memories. BRIEF SUMMARY Embodiments of a method for conducting read-verification operation of a memory cell in a three-dimensional (3D) memory device is described in the present disclosure. The invention is defined by the features of independent claims. Preferred embodiments are set out in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure. Fig. 1 illustrates a schematic top-down view of an exemplary three-dimensional (3D) memory die, according to some embodiments of the present disclosure.Fig. 2 illustrates a schematic top-down view of a region of 3D memory die, according to some embodiments of the present disclosure.Fig. 3 illustrates a perspective view of a portion of an exemplary 3D memory array structure, in accordance with some embodiments of the present disclosure.Fig. 4(a) illustrates a cross-sectional view of 3D memory cells, according to some embodiments of the present disclosure.Fig. 4(b) illustrates a schematic diagram of a 3D memory array, according to some embodiments of the present disclosure.Fig. 5 illustrates a timing diagram of a read-verification operation with a prepare voltage (pre-pulse) applied on a selected word line, according to some embodiments of the present disclosure.Figs. 6-8 illustrate timing diagrams of read-verification operations with accelerated fast charge loss, according to some embodiments of the present disclosure. The features and advantages of the present invention will become more apparent from the detailed description set forth below when taken in conjunction with the drawings, in which like reference characters identify corresponding elements throughout. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number. Embodiments of the present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications. It is noted that references in the specification to "one embodiment," "an embodiment," "an example embodiment," "some embodiments," etc., indicate that the embodiment described can include a particular feature, structure, or characteristic, but every embodiment can not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to affect such feature, structure or characteristic