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EP-4575806-B1 - COMPUTER SYSTEM AND PROCESS FOR PERFORMING RANDOM ACCESS OF A BIT IN A MEMORY

EP4575806B1EP 4575806 B1EP4575806 B1EP 4575806B1EP-4575806-B1

Inventors

  • XUE, Min

Dates

Publication Date
20260513
Application Date
20241217

Claims (14)

  1. A computer system comprising: - a data memory (MEM) configured to store a byte array (BTAB), and a program memory (MEMP) configured to store a computer program (PRG), - a digital signal processor (DSP) configured to execute a computer program (PRG) comprising instructions allowing accessing a bit in said byte array (BTAB), said digital signal processor (DSP) being configured to access each byte of said byte array, - a dedicated circuit (HWC) configured to read and/or write access a bit of a byte of said byte array using: • a bit position pointer (BITP) pointing towards the bit to be accessed in the byte array, and • said byte (BTE_IN) comprising the bit to be accessed, wherein the dedicated circuit (HWC) comprises: - a first block (NXTBBW) configured to calculate a byte shift value according to the value of the bit position pointer, and - a second block (READBIT) configured to determine the value of a bit to be read based on the bit position pointer (BITP) and a byte (BTE_IN) comprising said bit to be read, and wherein the computer program (PRG) comprises instructions which, when they are implemented by the digital signal processor, cause the latter to perform at least one call of a function (RD_BIT_NW) to read a bit in the byte array (BTAB), each call of this function taking as input the bit position pointer and a byte pointer as attributes and resulting in: - a calculation of a byte shift value by said first block (OFFST), then - an update of the byte pointer with said byte shift value, then - a determination of the value of the bit to be read by said second block (READBIT) of the dedicated circuit (HWC).
  2. The system according to claim 1, wherein the first block (NXTBBW) of the dedicated circuit (HWC) comprises: - an "AND" type logic gate (AND1) configured to perform an "AND" type logic operation between the value of the bit position pointer (BITP) and the hexadecimal value 0x7 to obtain an index value (INDX), - a comparison circuit (COMPC) configured to calculate the byte shift value by comparing the index value (INDX) with 0, the byte shift value being equal to -1 when the index value is equal to 0 and equal to 0 otherwise.
  3. The system according to any one of claims 1 or 2, wherein the second block (READBIT) of the dedicated circuit (HWC) comprises: - an adder circuit (ADD1) configured to increase the value of the bit position pointer by 1, - an "AND" type first logic gate (AND2) configured to perform an "AND" type logic operation between the increased value of the bit position pointer and a hexadecimal value equal to 0x7, - a subtractor circuit (SUB1) configured to calculate a shift value (SL) by subtracting a value equal to 7 from the value at the output of the "AND" type first logic gate (AND2), - a shift circuit (SFT1) configured to shift to the right the value of the byte comprising said bit to be accessed by a number of bits corresponding to said shift value (SL), - an "AND" type second logic gate (AND3) configured to perform an "AND" type logic operation between a value equal to 1 and the shifted value of the byte so as to obtain the value (BIT_OUT) of the bit to be read.
  4. The system according to one of claims 1 to 3, wherein the dedicated circuit (HWC) comprises a third block (WRITEBIT) configured to write the value of a bit instead of a bit pointed to by the bit position pointer (BITP) in a byte (BTE_IN) on which to write.
  5. The system according to claim 4, wherein the third block (WRITEBIT) of the dedicated circuit (HWC) comprises: - an adder circuit (ADD1) configured to increase the value of the bit position pointer by 1, - an "AND" type first logic gate (AND2) configured to perform an "AND" type logic operation between the increased value of the bit position pointer and a hexadecimal value equal to 0x7, - a subtractor circuit (SUB1) configured to calculate a shift value (SL) by subtracting a value equal to 7 from the value at the output of the "AND" type first logic gate (AND2), - a shift circuit (SFT2) configured to shift to the left the value 1 by a number of bits corresponding to said shift value (SL) to create a mask (MSK), - an inverter logic gate (NOT1) configured to create a complementary mask (INVMSK) based on said mask (MSK) obtained at the output of the shift circuit (SFT2), - an "AND" type second logic circuit (AND4) configured to apply the complementary mask (INVMSK) on the byte (BTE_IN) on which to write to obtain a first byte (B0), - an "OR" type logic circuit (OR1) configured to apply the mask (MSK) on the byte (BTE_IN) on which to write to obtain a second byte (B1), - a selection circuit (MUX1) configured to generate a byte (BTE_OUT) corresponding to the first byte (B0) if the value of the bit to be written is equal to 0 or corresponding to the second byte (B1) otherwise.
  6. The system according to any one of claims 4 or 5, wherein the computer program (PRG) comprises instructions which, when they are implemented by the digital signal processor, cause the latter to perform at least one call of a function (WRT_BIT_NW) to write a bit in the byte array (BTAB), each call of this function taking as input the bit position pointer and a byte pointer as attributes and resulting in: - a calculation of a byte shift value by said first block (OFFST), then - an update of the byte pointer with said byte shift value, then - a writing of the bit to be written by said third block (WRITEBIT) of the dedicated circuit (HWC).
  7. The system according to one of claims 1 to 6, wherein the computer program (PRG) comprises instructions which, when they are implemented by the digital signal processor (DSP), cause the latter to initiate the bit position pointer so that it points towards the position of the last bit of the byte array (BTAB), and to decrement said bit position pointer (BITP) at each read and/or write access.
  8. A method, implemented by a computer system (SYS), for read and/or write accessing a bit of a byte stored in a byte array (BTAB) in a data memory (MEM) of said computer system, the method comprising implementing instructions of the computer program (PRG) stored in a program memory (MEMP) by a digital signal processor (DSP) of the computer system (SYS) resulting in: - an access to said byte stored in the data memory (MEM) by the digital signal processor (DSP), - an implementation of a dedicated circuit (HWC) of the computer system (SYS) to read and/or write access said bit of the byte accessed by the digital signal processor (DSP) using: • a bit position pointer (BITP) pointing towards the bit to be accessed in the byte array, and • said byte (BTE_IN) comprising the bit to be accessed, the method further comprising: - implementing a first block (NXTBBW) of the dedicated circuit (HWC) to calculate a byte shift value (OFFST) according to the value of the bit position pointer (BITP), - implementing a second block (READBIT) of the dedicated circuit (HWC) to determine the value of a bit to be read based on the bit position pointer (BITP) and a byte (BTE_IN) comprising said bit to be read, and wherein the method further comprises implementing instructions of the computer program (PRG) by the digital signal processor (DSP) resulting in at least one call of a function (RD_BIT_NW) to read a bit in the byte array (BTAB), each call of this function taking as input the bit position pointer and a byte pointer as attributes and resulting in: - a calculation of a byte shift value by said first block (OFFST), then - an update of the byte pointer with said byte shift value, then - a determination of the value of the bit to be read by said second block (READBIT) of the dedicated circuit (HWC).
  9. The method according to claim 8, wherein the implementation of the first block (NXTBBW) of the dedicated circuit (HWC) results in: - an implementation of an "AND" type logic gate (AND1) of the first block (NXTBBW) to perform an "AND" type logic operation between the value of the bit position pointer (BITP) and the hexadecimal value 0x7 to obtain an index value (INDX), - an implementation of a comparison circuit (COMPC) of the first block (NXTBBW) to calculate the byte shift value by comparing the index value (INDX) with 0, the byte shift value being equal to -1 when the index value is equal to 0 and equal to 0 otherwise.
  10. The method according to one of claims 8 or 9, wherein the implementation of the second block (READBIT) of the dedicated circuit (HWC) results in: - an implementation of an adder circuit (ADD1) of the second block (READBIT) to increase the value of the bit position pointer by 1, - an implementation of an "AND" type first logic gate (AND2) of the second block (READBIT) to perform an "AND" type logic operation between the increased value of the bit position pointer and a hexadecimal value equal to 0x7, - an implementation of a subtractor circuit (SUB1) of the second block (READBIT) to calculate a shift value (SL) by subtracting a value equal to 7 from the value at the output of the "AND" type first logic gate (AND2), - an implementation of a shift circuit (SFT1) of the second block (READBIT) to shift to the right the value of the byte comprising said bit to be accessed by a number of bits corresponding to said shift value (SL), - an implementation of an "AND" type second logic gate (AND3) of the second block (READBIT) to perform an "AND" type logic operation between a value equal to 1 and the shifted value of the byte so as to obtain the value (BIT_OUT) of the bit to be read.
  11. The method according to one of claims 8 to 10, further comprising implementing a third block (WRITEBIT) of the dedicated circuit (HWC) to write the value of a bit instead of a bit pointed to by the bit position pointer (BITP) in a byte (BTE_IN) on which to write.
  12. The method according to claim 11, wherein the implementation of the third block (WRITEBIT) of the dedicated circuit (HWC) results in: - an implementation of an adder circuit (ADD1) of the third block (WRITEBIT) to increase the value of the bit position pointer by 1, - an implementation of an "AND" type first logic gate (AND2) of the third block (WRITEBIT) to perform an "AND" type logic operation between the increased value of the bit position pointer and a hexadecimal value equal to 0x7, - an implementation of a subtractor circuit (SUB1) of the third block (WRITEBIT) to calculate a shift value (SL) by subtracting a value equal to 7 from the value at the output of the "AND" type first logic gate (AND2), - an implementation of a shift circuit (SFT2) of the third block (WRITEBIT) to shift to the left the value 1 by a number of bits corresponding to said shift value (SL) to create a mask (MSK), - an implementation of an inverter logic gate (NOT1) of the third block (WRITEBIT) to create a complementary mask (INVMSK) based on said mask (MSK) obtained by implementation of the shift circuit (SFT2), - an implementation of an "AND" type second logic circuit (AND4) of the third block (WRITEBIT) to apply the complementary mask (INVMSK) on the byte (BTE_IN) on which to write to obtain a first byte (B0), - an implementation of an "OR" type logic circuit (OR1) of the third block (WRITEBIT) to apply the mask (MSK) on the byte (BTE_IN) on which to write to obtain a second byte (B1). - an implementation of a selection circuit (MUX1) to generate a byte (BTE_OUT) corresponding to the first byte (B0) if the value of the bit to be written is equal to 0 or corresponding to the second byte (B1) otherwise.
  13. The method according to any one of claims 11 or 12, comprising implementing instructions of the computer program (PRG) by the digital signal processor (DSP) resulting in at least one call of a function (WRT_BIT_NW) to write a bit in the byte array (BTAB), each call of this function taking as input the bit position pointer and a byte pointer as attributes and resulting in: - a calculation of a byte shift value by said first block (OFFST), then - an update of the byte pointer with said byte shift value, then - a writing of the bit to be written by said third block (WRITEBIT) of the dedicated circuit (HWC).
  14. The method according to one of claims 8 to 13, comprising implementing instructions of the computer program (PRG) by the digital signal processor (DSP) resulting in an initiation of the bit position pointer so that it points towards the position of the last bit of the byte array (BTAB), and in a decremention of said bit position pointer (BITP) at each read and/or write access.

Description

Some embodiments and implementation methods relate to the random reading and writing of a bit in a data memory of a computer system. A computer system may include a data memory configured to store an array of bytes and a central processing unit configured to read and/or write to that data memory in order to read or write words in said array of bytes. The central processing unit is usually configured to access data memory for reading and/or writing in order to read 8-bit, 16-bit, or 32-bit words. There are certain applications that require the random reading and/or writing of a bit from a byte array stored in a computer system's data memory. Random reading and/or writing refers to operations that occur at unpredictable times. Read and/or write accesses can be performed to read and/or write each bit of the byte array. For example, a well-known application that requires the random reading or writing of a bit from a data memory is the encoding and decoding of an audio signal. In these applications, 8-bit, 16-bit, or 32-bit memory accesses do not allow direct reading or writing of a bit into data memory. To access a single bit in the data memory byte array, it is common practice to access the byte of the byte array containing the bit to be accessed and then use a mask associated with the position of the bit to be accessed within that byte to select the bit. This bit access is performed in software by the central processing unit. Such a method requires multiple tests and updates to access a single bit. Specifically, the mask must be updated for each bit to be accessed. These software-based tests and updates can require several CPU cycles. Therefore, such bit access is relatively time-consuming. Furthermore, such bit access consumes a significant amount of energy due to the numerous CPU cycles required. However, for certain applications, particularly Bluetooth Low Energy (BLE), it is crucial to minimize energy consumption and the number of calculations required to perform a given task. US 2013/326201 A1 discloses a device and method for processing bit streams using dedicated "bit-oriented" instructions in a processor. Therefore, there is a need to propose a solution that allows simpler and faster access to a bit in a byte array. In one respect, a computer system is proposed comprising: a data memory configured to store an array of bytes, and a program memory configured to store a computer program, a digital signal processing unit configured to execute a computer program comprising instructions for accessing a bit in said byte array, said digital signal processing unit being configured to access each byte of said byte array, a dedicated circuit – notably integrated into the digital signal processing unit – configured to read and/or write to a bit of a byte of said byte array using: a bit position pointer pointing to the bit to be accessed in the byte array, and said byte containing the bit to be accessed. Such a computer system simply uses a bit position pointer, and not a byte position pointer taken in combination with a mask. Such a computer system is configured to access a bit in memory randomly using a dedicated circuit to execute certain instructions. This dedicated circuit occupies little space in the computer system and significantly improves the time required to access a bit in memory. Such a computer system is configured to access a bit in memory simply and quickly at random. Indeed, such a dedicated circuit requires few execution cycles of the digital signal processing unit to access a bit in memory randomly. Such a dedicated circuit also makes it possible to reduce the energy consumption for accessing a bit in memory randomly, because such access is carried out by performing few operations and in few cycles. In an advantageous embodiment, the dedicated circuit includes a first block configured to calculate a byte shift value according to the value of the bit position pointer. Advantageously, the first block of the dedicated circuit includes: an "AND" type logic gate configured to perform an "AND" type logical operation between the bit position pointer value and the hexadecimal value 0x7 to obtain an indexing value, a comparison circuit configured to calculate the byte offset value by comparing the index value to 0, the byte offset value being equal to -1 when the index value is equal to 0 and equal to 0 otherwise. In an advantageous embodiment, the dedicated circuit includes a second block configured to determine the value of a bit to be read from the bit position pointer and a byte comprising said bit to be read. Advantageously, the second block of the dedicated circuit includes: an adder circuit configured to increment the bit position pointer value by 1, a first "AND" type logic gate configured to perform a logical "AND" operation between the augmented value of the bit position pointer and a hexadecimal value equal to 0x7, a subtractor circuit configured to calculate an offset value by subtracting a