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EP-4578046-B1 - IMAGE SENSOR DEVICES INCLUDING A SUPERLATTICE AND RELATED METHODS

EP4578046B1EP 4578046 B1EP4578046 B1EP 4578046B1EP-4578046-B1

Inventors

  • TAKEUCHI, HIDEKI
  • CHEN, YI-ANN
  • CODY, NYLES WYNN

Dates

Publication Date
20260513
Application Date
20230816

Claims (15)

  1. An image sensor device (100, 100') comprising: a semiconductor substrate (101, 101'); a pixel region (102, 102') defining a pinned photodiode within the semiconductor substrate (101, 101') comprising a first dopant having a first conductivity type; deep trench isolation, DTI, regions (106, 106') surrounding the pixel region (102, 102'); a first pinning layer (103, 103') on a surface of the substrate (101, 101') and comprising a second dopant having a second conductivity type different to the first conductivity type; and a second pinning layer (105, 105') in the semiconductor substrate (101, 101') extending along the DTI regions (106, 106') and the pixel region (102, 102') and comprising a superlattice (25, 25') and the second dopant, the superlattice (25, 25') comprising a plurality of stacked groups of layers (45a-45n, 45a'-45n'), each group of layers comprising a plurality of stacked base semiconductor monolayers (46, 46') defining a base semiconductor portion (46a-46n, 46a'-46n'), and at least one non-semiconductor monolayer (50, 50') constrained within a crystal lattice of adjacent base semiconductor portions.
  2. The image sensor device (100, 100') of claim 1 wherein the second pinning layer (105, 105') extends along opposite sides of the pixel region (102, 102').
  3. The image sensor device (100, 100') of claim 2 wherein the second pinning layer (105, 105') extends along a bottom of the pixel region (102, 102').
  4. The image sensor device (100, 100') of claim 1 further comprising an isolation region in the semiconductor substrate (101, 101') adjacent the second pinning layer (105, 105,).
  5. The image sensor device (100, 100') of claim 4 wherein the second pinning layer (105, 105') wraps around the isolation region.
  6. The image sensor device (100, 100') of claim 1 wherein the first pinning layer (103, 103') is adjacent a first end of the pixel region (102, 102'); and further comprising a color filter layer (214) on the substrate adjacent a second end of the pixel region (102, 102') opposite the first end.
  7. The image sensor device (100, 100') of claim 6 further comprising a lens on the color filter layer (214).
  8. The image sensor device (100, 100') of claim 1 further comprising a transfer gate (210') adjacent the first pinning layer (103, 103'), a conductive contact (221') spaced apart from the transfer gate (210'), and a conductive via (222') extending between the transfer gate (210') and the conductive contact (221').
  9. The image sensor device (100, 100') of claim 1 wherein the second pinning layer (105, 105') further comprises fluorine.
  10. The image sensor device (100, 100') of claim 1 wherein the base semiconductor portion (46a-46n, 46a'-46n') comprises silicon.
  11. The image sensor device (100, 100') of claim 1 wherein the at least one non-semiconductor monolayer (50, 50') comprises oxygen.
  12. The image sensor device (100, 100') of claim 1 wherein the pixel region (102, 102') comprises a doped region (302a) including the first dopant, and an intrinsic region (302b) between the doped region (302a) and the second pinning layer (105, 105').
  13. The image sensor device (100, 100') of claim 12 wherein the superlattice (25, 25') comprises a first superlattice; and further comprising a second superlattice in the intrinsic region (302b), the superlattice (25, 25') comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
  14. The image sensor device (100, 100') of claim 13 wherein the second superlattice at least partially surrounds the doped region (302a).
  15. A method for making an image sensor device (100, 100') according to any of claims 1 to 14.

Description

Technical Field The present disclosure generally relates to semiconductor devices, and, more particularly, to semiconductor image sensor devices and related methods. Background Structures and techniques have been proposed to enhance the performance of semiconductor devices, such as by enhancing the mobility of the charge carriers. For example, U.S. Patent Application No. 2003/0057416 to Currie et al. discloses strained material layers of silicon, silicon-germanium, and relaxed silicon and also including impurity-free zones that would otherwise cause performance degradation. The resulting biaxial strain in the upper silicon layer alters the carrier mobilities enabling higher speed and/or lower power devices. Published U.S. Patent Application No. 2003/0034529 to Fitzgerald et al. discloses a CMOS inverter also based upon similar strained silicon technology. U.S. Patent No. 6,472,685 B2 to Takagi discloses a semiconductor device including a silicon and carbon layer sandwiched between silicon layers so that the conduction band and valence band of the second silicon layer receive a tensile strain. Electrons having a smaller effective mass, and which have been induced by an electric field applied to the gate electrode, are confined in the second silicon layer, thus, an n-channel MOSFET is asserted to have a higher mobility. U.S. Patent No. 4,937,204 to Ishibashi et al. discloses a superlattice in which a plurality of layers, less than eight monolayers, and containing a fractional or binary or a binary compound semiconductor layer, are alternately and epitaxially grown. The direction of main current flow is perpendicular to the layers of the superlattice. U.S. Patent No. 5,357,119 to Wang et al. discloses a Si-Ge short period superlattice with higher mobility achieved by reducing alloy scattering in the superlattice. Along these lines, U.S. Patent No. 5,683,934 to Candelaria discloses an enhanced mobility MOSFET including a channel layer comprising an alloy of silicon and a second material substitutionally present in the silicon lattice at a percentage that places the channel layer under tensile stress. U.S. Patent No. 5,216,262 to Tsu discloses a quantum well structure comprising two barrier regions and a thin epitaxially grown semiconductor layer sandwiched between the barriers. Each barrier region consists of alternate layers of SiO2/Si with a thickness generally in a range of two to six monolayers. A much thicker section of silicon is sandwiched between the barriers. An article entitled "Phenomena in silicon nanostructure devices" also to Tsu and published online September 6, 2000 by Applied Physics and Materials Science & Processing, pp. 391-402 discloses a semiconductor-atomic superlattice (SAS) of silicon and oxygen. The Si/O superlattice is disclosed as useful in a silicon quantum and light-emitting devices. In particular, a green electroluminescence diode structure was constructed and tested. Current flow in the diode structure is vertical, that is, perpendicular to the layers of the SAS. The disclosed SAS may include semiconductor layers separated by adsorbed species such as oxygen atoms, and CO molecules. The silicon growth beyond the adsorbed monolayer of oxygen is described as epitaxial with a fairly low defect density. One SAS structure included a 1.1 nm thick silicon portion that is about eight atomic layers of silicon, and another structure had twice this thickness of silicon. An article to Luo et al. entitled "Chemical Design of Direct-Gap Light-Emitting Silicon" published in Physical Review Letters, Vol. 89, No. 7 (August 12, 2002) further discusses the light emitting SAS structures of Tsu. U.S. Pat. No. 7,105,895 to Wang et al. discloses a barrier building block of thin silicon and oxygen, carbon, nitrogen, phosphorous, antimony, arsenic or hydrogen to thereby reduce current flowing vertically through the lattice more than four orders of magnitude. The insulating layer/barrier layer allows for low defect epitaxial silicon to be deposited next to the insulating layer. Published Great Britain Patent Application 2,347,520 to Mears et al. discloses that principles of Aperiodic Photonic Band-Gap (APBG) structures may be adapted for electronic bandgap engineering. In particular, the application discloses that material parameters, for example, the location of band minima, effective mass, etc., can be tailored to yield new aperiodic materials with desirable band-structure characteristics. Other parameters, such as electrical conductivity, thermal conductivity and dielectric permittivity or magnetic permeability are disclosed as also possible to be designed into the material. Furthermore, U.S. Pat. No. 6,376,337 to Wang et al. discloses a method for producing an insulating or barrier layer for semiconductor devices which includes depositing a layer of silicon and at least one additional element on the silicon substrate whereby the deposited layer is substantially free of defects such that epitaxial silic