EP-4579664-B1 - UNIVERSAL LOGIC MEMORY CELL

EP4579664B1EP 4579664 B1EP4579664 B1EP 4579664B1EP-4579664-B1

Inventors

KIM, SANG SIG
CHO, KYOUNG AH
HAN, JONG SEONG
SON, JAE MIN
JEON, Ju Hee
SHIN, YUN WOO

Dates

Publication Date: 20260513
Application Date: 20241114

Claims (12)

A universal logic memory cell, comprising a first network device and a second network device using a plurality of triple-gate silicon devices, wherein each of the triple-gate silicon devices comprises a drain region, a channel region, and a source region; a supply voltage is applied to the drain region and the source region; a gate region on which first and second programming gate electrodes and a control gate electrode are formed is formed on the channel region; depending on a level of a program voltage (V PG ) applied through the first and second programming gate electrodes, the channel region under the first and second programming gate electrodes operates in one of a first channel mode and a second channel mode; and the triple-gate silicon device is determined to be in either an on-state or an off-state based on a level of a control voltage (V CG ) applied through the control gate electrode, and wherein, when the channel region under the first and second programming gate electrodes operates in the first channel mode, each of the triple-gate silicon devices is determined to be in an on-state when a level of the applied control gate voltage (V CG ) is higher than a latch-up voltage, which is a voltage at which current increases rapidly, and is determined to be in an off-state when a level of the applied control gate voltage (V CG ) is lower than the latch-up voltage, wherein the first and second network devices are composed of a first parallel connection formed by connecting common drain regions between a first serial connection in which the drain regions and source regions of two of four triple-gate silicon devices are connected in series and a second serial connection in which the drain regions and source regions of the remaining two triple-gate silicon devices are connected in series and a second parallel connection formed by connecting common source regions therebetween, a drain voltage (V DD ) of the common voltage is applied through the first parallel connection of the first network device, a source voltage (V SS ) of the common voltage is applied through the second parallel connection of the second network device, and an output voltage (V OUT ) is measured at a point where the second parallel connection of the first network device and the first parallel connection of the second network device are connected, characterized in that the first and second network devices perform a ternary logic operation function and a memory function by determining a level of an output voltage (V OUT ) as one of a positive level, a zero level, and a negative level depending on any one of the states in any one of the channel modes, wherein, when the first network device operates in the second channel mode and the second network device operates in the first channel mode, the ternary logic operation function of determining a level of the output voltage (V OUT ) as a positive level when a level of the control voltage (V CG ) is a negative level, determining a level of the output voltage (V OUT ) as a negative level when a level of the control voltage (V CG ) is a positive level, and determining a level of the output voltage (V OUT ) as a zero level when a level of the control voltage (V CG ) is a zero level is performed.
The universal logic memory cell according to claim 1, wherein, when the first network device operates in the first channel mode and the second network device operates in the second channel mode, the ternary logic operation function of determining a level of the output voltage (V OUT ) as a negative level when a level of the control voltage (V CG ) is a negative level, determining a level of the output voltage (V OUT ) as a positive level when a level of the control voltage (V CG ) is a positive level, and determining a level of the output voltage (V OUT ) as a zero level when a level of the control voltage (V CG ) is a zero level is performed.
The universal logic memory cell according to claim 1, wherein the ternary logic operation function of determining a level of the output voltage (V OUT ) as a positive level when the first network device operates in the second channel mode, the second network device operates in the first channel mode, a first control voltage (V IN1 ) of the control voltage (V CG ) is applied to a left side of the first network device and an upper side of the second network device, a second control voltage (V IN2 ) of the control voltage (V CG ) is applied to a right side of the first network device and a lower side of the second network device, and any one level of levels of the first control voltage (V IN1 ) and the second control voltage (V IN2 ) is a negative level, determining a level of the output voltage (V OUT ) as a negative level when levels of the first control voltage (V IN1 ) and the second control voltage (V IN2 ) are both positive levels, and determining a level of the output voltage (V OUT ) as a zero level when levels of the first control voltage (V IN1 ) and the second control voltage (V IN2 ) are both zero levels or one level is a zero level and the other level is a positive level is performed.
The universal logic memory cell according to claim 1, wherein the ternary logic operation function of determining a level of the output voltage (V OUT ) as a negative level when the first network device operates in the second channel mode, the second network device operates in the first channel mode, a first control voltage (V IN1 ) of the control voltage (V CG ) is applied to an upper side of the first network device and a left side of the second network device, a second control voltage (V IN2 ) of the control voltage (V CG ) is applied to a lower side of the first network device and a right side of the second network device, and any one level of levels of the first control voltage (V IN1 ) and the second control voltage (V IN2 ) is a positive level, determining a level of the output voltage (V OUT ) as a positive level when levels of the first control voltage (V IN1 ) and the second control voltage (V IN2 ) are both negative levels, and determining a level of the output voltage (V OUT ) as a zero level when levels of the first control voltage (V IN1 ) and the second control voltage (V IN2 ) are both zero levels or one level is a zero level and the other level is a negative level is performed.
The universal logic memory cell according to claim 1, wherein the ternary logic operation function of determining a level of the output voltage (V OUT ) as a negative level when the first network device operates in the first channel mode, the second network device operates in the second channel mode, a first control voltage (V IN1 ) of the control voltage (V CG ) is applied to an upper side of the first network device and a left side of the second network device, a second control voltage (V IN2 ) of the control voltage (V CG ) is applied to a lower side of the first network device and a right side of the second network device, and any one level of levels of the first control voltage (V IN1 ) and the second control voltage (V IN2 ) is a negative level, determining a level of the output voltage (V OUT ) as a positive level when levels of the first control voltage (V IN1 ) and the second control voltage (V IN2 ) are both positive levels, and determining a level of the output voltage (V OUT ) as a zero level when levels of the first control voltage (V IN1 ) and the second control voltage (V IN2 ) are both zero levels or any one level is a zero level and the other level is a positive level is performed.
The universal logic memory cell according to claim 1, wherein the ternary logic operation function of determining a level of the output voltage (V OUT ) as a positive level when the first network device operates in the second channel mode, the second network device operates in the first channel mode, a first control voltage (V IN1 ) of the control voltage (V CG ) is applied to a left side of the first network device and an upper side of the second network device, a second control voltage (V IN2 ) of the control voltage (V CG ) is applied to a right side of the first network device and a lower side of the second network device, and any one level of levels of the first control voltage (V IN1 ) and the second control voltage (V IN2 ) is a positive level, determining a level of the output voltage (V OUT ) as a negative level when levels of the first control voltage (V IN1 ) and the second control voltage (V IN2 ) are both negative levels, and determining a level of the output voltage (V OUT ) as a zero level when levels of the first control voltage (V IN1 ) and the second control voltage (V IN2 ) are both zero levels or any one level is a zero level and the other level is a negative level is performed.
The universal logic memory cell according to claim 1, wherein the ternary logic operation function of determining a level of the output voltage (V OUT ) as a positive level when a left side of the first network device operates in the first channel mode, a right side of the first network device operates in the second channel mode, an upper left side of the second network device operates in the second channel mode, an upper right side of the second network device operates in the first channel mode, a lower left side of the second network device operates in the first channel mode, a lower right side of the second network device operates in the second channel mode, a first control voltage (V IN1 ) of the control voltage (V CG ) is applied to an upper side of the first and second network devices, a second control voltage (V IN2 ) of the control voltage (V CG ) is applied to a lower side of the first and second network devices, and levels of the first control voltage (V IN1 ) and the second control voltage (V IN2 ) are both negative or positive levels, determining a level of the output voltage (V OUT ) as a negative level when levels of the first control voltage (V IN1 ) and the second control voltage (V IN2 ) are opposite to each other and are negative or positive levels, and determining a level of the output voltage (V OUT ) as a zero level when any one level of levels of the first control voltage (V IN1 ) and the second control voltage (V IN2 ) is a zero level is performed.
The universal logic memory cell according to claim 1, wherein the ternary logic operation function of determining a level of the output voltage (V OUT ) as a negative level when an upper left side of the first network device operates in the second channel mode, an upper right side of the first network device operates in the first channel mode, a lower left side of the first network device operates in the first channel mode, a lower right side of the first network device operates in the second channel mode, a left side of the second network device operates in the first channel mode, a right side of the second network device operates in the second channel mode, a first control voltage (V IN1 ) of the control voltage (V CG ) is applied to an upper side of the first and second network devices, a second control voltage (V IN2 ) of the control voltage (V CG ) is applied to a lower side of the first and second network devices, and levels of the first control voltage (V IN1 ) and the second control voltage (V IN2 ) are both positive levels, determining a level of the output voltage (V OUT ) as a negative level when levels of the first control voltage (V IN1 ) and the second control voltage (V IN2 ) are both negative levels, outputting a level of the output voltage (V OUT ) as a positive level when levels of the first control voltage (V IN1 ) and the second control voltage (V IN2 ) are opposite to each other and are negative or positive levels, and determining a level of the output voltage (V OUT ) as a zero level when either of levels of the first control voltage (V IN1 ) and the second control voltage (V IN2 ) is a zero level is performed.
The universal logic memory cell according to claim 1, wherein the drain region is in a p-doped state; the source region is in an n-doped state; the channel region is in an intrinsic state; and the channel region under the first and second programming gate electrodes operates as an n-channel corresponding to the first channel mode when a level of the program voltage (V PG ) is a positive level and operates as a p-channel corresponding to the second channel mode when a level of the program voltage (V PG ) is a negative level.
The universal logic memory cell according to claim 1, wherein, when a drain voltage (V DD ) applied to the drain region, a source voltage (V SS ) applied to the source region, the program voltage (V PG ), and the control voltage (V CG ) are applied at a zero level, the memory function is performed by maintaining a level of the output voltage (V OUT ).
The universal logic memory cell according to one of claims 1 to 10, wherein, when the channel region under the first and second programming gate electrodes operates in the first channel mode and a level of the applied control voltage (V CG ) is higher than the latch-up voltage, each of the triple-gate silicon devices has a lowered potential barrier height between the channel region under the control gate electrode and the channel region under the second programming gate electrode adjacent to the source region and becomes the on-state, where current flows due to a first positive feedback loop in which electrons are injected from the source region due to the lowered potential barrier.
The universal logic memory cell according to one of claims 1 to 11, wherein, when the channel region under the first and second programming gate electrodes operates in the second channel mode, each of the triple-gate silicon devices is determined to be in an off-state when a level of the applied control gate voltage (V CG ) is higher than a latch-up voltage, which is a voltage at which current increases rapidly, and is determined to be in an on-state when a level of the applied control gate voltage (V CG ) is lower than the latch-up voltage, wherein, when the channel region under the first and second programming gate electrodes operates in the second channel mode, when a level of the applied control voltage (V CG ) is lower than the latch-up voltage, each of the triple-gate silicon devices has a lowered potential barrier height between the channel region under the control gate electrode and the channel region under the first programming gate electrode adjacent to the drain region and becomes the on-state, where current flows due to a second positive feedback loop in which holes are injected from the drain region due to the lowered potential barrier.

Description

BACKGROUND OF THE DISCLOSURE Field of the Disclosure The present disclosure relates to a universal logic memory cell composed of triple-gate silicon devices, and more particularly, to technology for implementing a universal logic memory cell that provides ternary logic operation function and memory function using a triple-gate silicon device driven by a positive feedback loop. Description of the Related Art KR 102 475 066 is related to a reconfigurable logic-in-memory cell comprising a triple gate feedback memory device. The reconfigurable logic-in-memory cell provides a logical operation function and a memory function by using the triple gate feedback memory device. The reconfigurable logic-in-memory cell includes a drain area, a channel area, and a source area. The channel area includes multiple triple gate feedback memory devices including a gate area having first and second programming gate electrodes and a control gate electrode. The channel area under the first and second programming gate electrodes performs either an n-channel operation or a p-channel operation depending on a level of a program voltage applied through the first and second programming gate electrodes. Also, each of the multiple triple gate feedback memory devices either assumes an on-state or an off-state based on the level of a control voltage applied through the control gate electrode. Each of the multiple triple gate feedback memory devices can perform the logical operation function and the memory function based on the level of an output voltage changed according to the state of the performed channel operation. KR 2023 0053195 A is related to a stateful logic-in-memory using silicon diodes. The device comprises a plurality of silicon diodes each of which serves as a memory cell and includes an anode region, a first channel region, a second channel region, and a cathode region. In each memory cell, a terminal of the cathode region is connected in parallel with a terminal of the other cathode region and then connected in series with a resistor, and each memory cell receives an operating voltage through a terminal of the anode region. The plurality of memory cells includes at least one input cell and one output cell and performs an implication (IMP) operation at least once based on the applied operating voltage and states of the at least one input cell and the output cell. The plurality of memory cells can perform a logical operation function and a memory function by changing or maintaining the state of the output cell based on the IMP operation performed at least once. US 2023/170907 A discloses an inverter which includes a first P-MOS transistor connected between a node receiving a drain voltage and a first path node, which is operated based on an input voltage, a first N-MOS transistor connected between the first path node and an output terminal outputting an output voltage, which is operated based on the drain voltage, a second P-MOS transistor connected between the output terminal and a second path node, which is operated based on a ground voltage, a second N-MOS transistor connected between the second path node and a node receiving the ground voltage, which is operated based on the input voltage, a third P-MOS transistor connected between the first path node and the second path nod, which is operated based on the input voltage, and a third N-MOS transistor connected between the first path node and the second path node, which is operated based on the input voltage. In existing von Neumann-based computer systems, a processor and a memory are separated and data is transmitted through a bus. However, as computing performance improved, bottlenecks occurred due to the difference in data processing speed between the processor and memory, and limitations in processing large amounts of data began to appear. That is, the von Neumann-based system, a revolutionary development in the semiconductor industry, improved the integration density and performance of modern computers, but the von Neumann-based system has the disadvantages of consuming a lot of energy and having long data transmission time and latency time due to the physical separation between the processor and memory hierarchy. Given the increase of data-intensive applications such as 5G communication standards, the Internet of Things (IoT), and artificial intelligence (AI) following the Fourth Industrial Revolution, new computing paradigms are essential to meet massive data processing requirements. To solve the above-mentioned problems, research on logic memory technology that combines computational and memory functions is being focused and accelerated. Since the logic memory technology performs the computational function of a processor and the memory function of a memory in the same space, the logic memory technology can reduce delay time and power consumption that occur during data transmission and greatly improve the integration of a system. Conventional logic memory technology