Search

EP-4580064-B1 - ANALOG-TO-DIGITAL CONVERTER, SYSTEM-ON-CHIP AND ELECTRONIC CONTROL SYSTEM

EP4580064B1EP 4580064 B1EP4580064 B1EP 4580064B1EP-4580064-B1

Inventors

  • YANG, QINGQING
  • WANG, CONG

Dates

Publication Date
20260513
Application Date
20240708

Claims (15)

  1. An analog-to-digital converter (ADC), comprising: a sequence management circuit (25), which is configured to, after the ADC (2) is triggered and activated, load a target sequence count for a streaming access mode and generate a multi-channel input control signal and a sequence selection output control signal, the sequence management circuit (25) is further configured to generate a stream interrupt signal when an actual sequence count kept in the ADC (2) reaches the target sequence count; a multi-channel input multiplexer (21), which is coupled to the sequence management circuit (25) and is configured to receive an analog signal to be converted and, under the control of the multi-channel input control signal, sequentially strobe associated input channel(s) according to a designated conversion priority order designated by each sequence, thereby generating a sample sequence; an analog-to-digital conversion (ADC) circuit, which is coupled to the multi-channel input multiplexer (21) and is configured to convert the sample sequence into a corresponding digital sequence; a sequence output multiplexer (23), which is coupled to the ADC circuit (22) and a sequence data register (24) and is configured to store the digital sequence output from the ADC circuit (22) into the sequence data register (24) according to a specified sequence sorting scheme under the control of the sequence selection output control signal; and an interrupt generation circuit (26), which is coupled to the sequence management circuit (25) and an associated interrupt controller (3) and is configured to notify the interrupt controller (3) to perform an interrupt processing on the ADC (2) when the stream interrupt signal is valid, characterized in that : wherein the sequence management circuit (25) comprises a streaming access circuit (252), which is configured to load the target sequence count automatically or by software after the ADC (2) is triggered and activated and to generate the stream interrupt signal when the actual sequence count kept in the ADC (2) reaches the target sequence count; the streaming access circuit (252) comprising a stream enable bit (2521), which enables the streaming access mode for the ADC (2) when set valid, or disables the streaming access mode for the ADC (2) when set invalid; after the ADC (2) is triggered and activated, when the stream enable bit (2521) is set valid, the streaming access mode of the ADC (2) is enabled, allowing the ADC (2) to support processing of a preset number of sequences.
  2. The ADC (2) of claim 1, wherein the sequence management circuit (25) further comprises: a sequence sorter (251), which is configured to, for each sequence, configure the designated conversion priority order designated by each sequence and configure the sequence sorting scheme before the actual sequence count kept in the ADC (2) reaches the target sequence count; and a control signal generation circuit (250), which is coupled to the streaming access circuit (252) and the sequence sorter (251) and is configured to generate the multi-channel input control signal and the sequence selection output control signal according to the conversion priority order configured by the sequence sorter (251) before the actual sequence count kept in the ADC (2) reaches the target sequence count.
  3. The ADC (2) of claim 2, wherein the streaming access circuit (252) further comprises: a counting circuit (2524), which is coupled to the stream enable bit (2521) and is configured to load the target sequence count during initialization of the ADC (2) in the streaming access mode and to calculate a difference between the actual sequence count kept in the ADC (2) and the target sequence count; and a stream interrupt flag bit (2528), which is coupled to the counting circuit (2524) and is configured to be set valid when the difference becomes 0 in the streaming access mode.
  4. The ADC (2) of claim 3, wherein the streaming access circuit (252) further comprises: a comparator (2526), which comprises an input terminal coupled to the counting circuit (2524) and an output terminal coupled to the stream interrupt flag bit (2528) and is configured to determine whether the difference becomes 0 in the streaming access mode; a stream interrupt enable bit (2527), which enables an interrupt in the streaming access mode when set valid, or disables an interrupt in the streaming access mode when set invalid; and a stream interrupt generation circuit (2529), which is coupled to the stream interrupt flag bit (2528) and the stream interrupt enable bit (2527) and is configured to perform a logic AND operation on the stream interrupt enable bit (2527) and the stream interrupt flag bit (2528) to generate the stream interrupt signal which is valid or invalid.
  5. The ADC (2) of claim 3, wherein the counting circuit (2524) comprises: a stream counter register (2524a), which is coupled to the stream enable bit (2521) and is configured to load the target sequence count during the initialization of the ADC (2) in the streaming access mode; and a counter (2524b), which is coupled to the stream counter register (2524a) and is configured to, in the streaming access mode, decrement the target sequence count stored in the stream counter register (2524a) by 1 in response to completion of processing of each sequence by the ADC (2).
  6. The ADC (2) of claim 3, wherein the streaming access circuit (252) further comprises a stream counter auto-reload enable bit (2522), which enables the counting circuit (2524) to automatically reload the target sequence count when the stream counter auto-reload enable bit (2522) is set valid and when the difference becomes 0, or disables the counting circuit (2524) from automatically reloading the target sequence count when the stream counter auto-reload enable bit (2522) is set invalid and when the difference becomes 0; optionally wherein the streaming access circuit (252) further comprises a stream counter mode selection bit (2523), which, when set invalid, allows the ADC circuit (22) to continue converting the sample sequence to the digital sequence if the difference becomes 0, or, when set valid, allows the streaming access circuit (252) to automatically reload the target sequence count and allows the ADC circuit (22) to continue converting the sample sequence to the digital sequence upon the difference becoming 0 if the stream counter auto-reload enable bit (2522) is also set valid, or prevents the ADC circuit (22) from converting the sample sequence to the digital sequence and causes the target sequence count to be reloaded by the software after the ADC (2) is interrupted according to the set stream interrupt flag bit (2528) upon the difference becoming 0 if the stream counter auto-reload enable bit (2522) is set invalid.
  7. The ADC (2) of claim 1, further comprising a trigger selection circuit (20), which is coupled to the sequence management circuit (25) and is configured to receive an associated software trigger signal and/or hardware trigger signal and activate operation of the sequence management circuit (25) according to the received software trigger signal and/or hardware trigger signal.
  8. The ADC (2) of any one of claims 1 to 7, wherein the streaming access mode is a circular streaming access mode, or a linear streaming access mode; in the circular streaming access mode, when the sequence data register (24) becomes full, the sequence output multiplexer (23) stores each subsequent digital sequence into the sequence data register (24) in a first-in first-out (FIFO) fashion; and in the linear streaming access mode, when the actual sequence count reaches the target sequence count, the sequence output multiplexer (23) does not store any new digital sequence into the sequence data register (24).
  9. The ADC (2) of any one of claims 1 to 8, wherein during the storage of the digital sequence into the sequence data register (24) according to the specified sequence sorting scheme by the sequence output multiplexer (23), n digital sequences are kept in the sequence data register (24), and the sequence output multiplexer (23) overrides the earliest one of the digital sequences in the sequence data register (24) with the digital sequence to ensure that the n digital sequences stored in the sequence data register (24) always constitute the latest combination.
  10. A system-on-chip (SoC), comprising the ADC (2) of any one of claims 1 to 9.
  11. The SoC of claim 10, wherein the SoC is an analog-to-digital conversion (ADC) chip, the ADC chip coupled to a microcontroller unit (MCU) chip disposed outside of the SoC and comprising an interrupt controller (3), or wherein the SoC is an MCU chip, the MCU chip comprising, integrated on a chip body, an MCU core (6), an interrupt controller (3), an input/output (I/O) interface (1) and the ADC (2), the I/O interface (1) coupled to the ADC (2) and configured to provide an analog signal to the ADC (2), the MCU core (6) coupled to the ADC (2) and configured to configure signals in the ADC (2) and access and process a digital sequence in the sequence data register (24) of the ADC (2), the interrupt controller (3) coupled to an output terminal of the ADC (2) and the MCU core (6) and configured to, when receiving a valid interrupt signal output from the ADC (2), raise an interrupt request to the MCU core (6), which requires the MCU core (6) to interrupt the ADC (2); optionally wherein the SoC further comprises a direct memory access (DMA) controller (4) and a data cache (5), the DMA controller (4) configured to transfer a digital sequence stored in the sequence data register (24) of the ADC (2) to the data cache (5), wherein the MCU core (6) directly accesses the data cache (5) to process the digital sequence stored in the data cache (5).
  12. The SoC of claim 10 or 11, wherein the MCU core (6) comprises a sliding average filtering module (60), the sliding average filtering module (60) configured to perform a sliding average filtering operation on n data read from the sequence data register (24) of the ADC (2) or from the data cache (5) to calculate an average thereof, where n is the integer greater than 1.
  13. The SoC of claim 10 or 11, further comprising a timer (7), which is coupled to the ADC (2) and is configured to generate, at a predetermined time interval, hardware trigger signals for triggering sequence sampling and conversion of the ADC (2).
  14. An electronic control system, comprising the SoC of any one of claims 10 to 13.
  15. The electronic control system of claim 14, wherein the electronic control system is used to control a brushless direct-current (BLDC) motor (9), the electronic control system further comprising a three-phase inverter (8), a speed detection circuit (11) and a current detection circuit (10), the three-phase inverter (8) coupling the MCU core (6) in the SoC to the BLDC motor (9), the speed detection circuit (11) coupled to the BLDC motor (9) and configured to detect a rotating speed of the BLDC motor (9) and provide the detected speed to the MCU core (6), the current detection circuit (10) coupled to the BLDC motor (9) and configured to detect a current in the BLDC motor (9) and provide the detected current to the ADC (2) in the SoC as an analog signal to be converted, wherein the MCU core (6) is based on the detected speed and a digital sequence output from the ADC (2) to drive the three-phase inverter (8) to modify the rotating speed and current of the BLDC motor (9); optionally wherein the MCU core (6) comprises a sliding average filtering module (60), a speed loop regulator (62), a current loop regulator (64), a pulse-width modulation (PWM) controller (65), a first superimposer (61) and a second superimposer (63), the first superimposer (61) coupled to the speed detection circuit (11) and configured to superimpose the detected speed with an associated given speed, the speed loop regulator (62) configured to generate a speed regulation signal based on an output of the first superimposer (61), the sliding average filtering module (60) configured to generate an average current value based on the digital sequence output from the ADC (2), the second superimposer (63) coupled to the speed loop regulator (62) and the sliding average filtering module (60) and configured to superimpose the average current value with the speed regulation signal, the current loop regulator (64) configured to generate a regulation signal based on an output of the second superimposer (63), the PWM controller (65) configured to generate, based on the regulation signal output from the second superimposer (63), a drive signal for driving operation of the three-phase inverter (8).

Description

TECHNICAL FIELD The present invention relates to the field of electronic systems and, in particular, to an analog-to-digital converter (ADC), a system-on-chip (SoC) and an electronic control system. BACKGROUND An analog-to-digital converter (ADC) is mainly used to convert an analog signal, such as voltage, current, pressure, temperature, humidity, displacement or sound, into its digital representation for subsequent processing in an electronic system. There is an increasing demand for ADCs with higher performance that can meet the requirements stemming from the ever-advancing digital communication, digital signal processing, digital measurement, MCU and other techniques, the increasing operating speed of electronic systems and an ever-increasing demand for higher sensitivity of electronic systems. However, existing ADCs, either integrated in or attached to a microcontroller unit (MCU) chip, only support conversion of each sequence (including at least one channel) in a one-shot conversion mode or a continuous conversion mode. Moreover, after the conversion of each sequence is completed, an interrupt request is generated to allow the MCU to process the converted digital signal using an appropriate data processing algorithm. Accordingly, in order to convert a preset number of sequences, an interrupt is generated after the conversion of each sequence is completed. Such multiple interrupts disrupt execution of the data processing algorithm in the MCU, thus adversely affecting its signal processing performance and speed, and hence the real-time control and operation of the electronic control system incorporating the MCU. US 6 486 809 B1 discloses a digital system incorporating an analog-to-digital converter (ADC) configured to permit a programmable number of automatic conversions on two separate and independent, yet cascadeable, sequencers. Ti: "TMS320LF2401A, TMS320LC2401A DSP CONTROLLERS",, 1 July 2007 (2007-07-01), pages 1-89, relates to a digital signal processor controller, that includes an analog-to-digital converter and an event manager module optimized for digital motor control and power conversion applications. SUMMARY OF THE INVENTION It is an objective of the present invention to provide an analog-to-digital converter (ADC), a system-on-chip (SoC) and an electronic control system. The ADC is enabled by hardware to process a preset number of sequences and can process sample data in a streaming access mode, without being interrupted to check whether an actual sequence count kept in the ADC reaches a target sequence count at the end of processing of each sequence. This overcomes the disadvantages arising from frequent interrupts, in particular in high-frequency applications requiring an ADC to process sequences at a very high speed (especially when a small number of channels are designated for or included in each sequence). The ADC can avoid untimely interrupt response that may occur due to the generation of a new interrupt during an ongoing interrupt. To this end, the present invention provides an ADC including: a sequence management circuit, which is configured to load a target sequence count for a streaming access mode and generate a multi-channel input control signal and a sequence selection output control signal after the ADC is triggered and activated and to generate a stream interrupt signal when an actual sequence count kept in the ADC reaches the target sequence count;a multi-channel input multiplexer, which is coupled to the sequence management circuit and is configured to receive an analog signal to be converted and, under the control of the multi-channel input control signal, sequentially strobe associated input channel(s) according to a designated conversion priority order designated by each sequence, thereby generating a sample sequence;an analog-to-digital conversion (ADC) circuit, which is coupled to the multi-channel input multiplexer and is configured to convert the sample sequence into a corresponding digital sequence;a sequence output multiplexer, which is coupled to the ADC circuit and a sequence data register and is configured to store the digital sequence output from the ADC circuit into the sequence data register according to a specified sequence sorting scheme under the control of the sequence selection output control signal; andan interrupt generation circuit, which is coupled to the sequence management circuit and an associated interrupt controller and is configured to notify the interrupt controller when the stream interrupt signal is valid, which then interrupts the ADC. Compared with the prior art, in addition to hardware circuits commonly found in conventional ADCs, including the multi-channel input multiplexer, the ADC circuit, the sequence output multiplexer and the sequence data register, the ADC further includes the sequence management circuit and the interrupt generation circuit, which have been improved. Specifically, after the ADC enters the streaming access mode, the