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EP-4642184-B1 - SEMICONDUCTOR DEVICES

EP4642184B1EP 4642184 B1EP4642184 B1EP 4642184B1EP-4642184-B1

Inventors

  • KIM, Junsoo
  • OH, JEONGHOON
  • JANG, SUNGHO

Dates

Publication Date
20260513
Application Date
20250225

Claims (15)

  1. A semiconductor device, comprising: a bit line structure (110); charge trapping structures (120) on the bit line structure (110); word line structures (150) arranged alternately with the charge trapping structures (120) in a first direction (X), each of the word line structures (150) including a first word line (152a) and a second word line (152b) spaced apart from each other in the first direction (X); active patterns (140) arranged on the bit line structure (110), arranged between the charge trapping structures (120) and the word line structures (150), and electrically connected to the bit line structure (110); contact patterns (170) arranged on the active patterns (140) and electrically connected to the active patterns (140); and an information storage structure (180) on the contact patterns (170), wherein each of the charge trapping structures (120) includes: at least one charge trapping layer (122) between the active patterns (140); and first insulating films (121) between the at least one charge trapping layer (122) and the active patterns (140).
  2. The semiconductor device of claim 1, wherein the first insulating films (121) include a first insulating material, and wherein the at least one charge trapping layer (122) includes a second insulating material different from the first insulating material.
  3. The semiconductor device of claim 2, wherein the first insulating material includes oxide, and wherein the second insulating material includes nitride.
  4. The semiconductor device of any one of claims 1 to 3, wherein the at least one charge trapping layer (122) includes a first charge trapping layer (122a) and a second charge trapping layer (122b) spaced apart from each other in the first direction (X).
  5. The semiconductor device of claim 4, wherein widths of each of the first insulating films (121) in the first direction (X) are greater than a width of the first charge trapping layer (122a) and greater than a width of the second charge trapping layer (122b).
  6. The semiconductor device of claim 4 or 5, wherein each of the charge trapping structures (120) further includes a second insulating film (123) between the first charge trapping layer (122a) and the second charge trapping layer (122b).
  7. The semiconductor device of claim 6, wherein a width of the second insulating film (123) in the first direction (X) is greater than respective widths of each of the first insulating films (121) in the first direction (X).
  8. The semiconductor device of claim 4, wherein each of the charge trapping structures (120) further includes a conductive film (125) between the first charge trapping layer (122a) and the second charge trapping layer (122b).
  9. The semiconductor device of claim 8, wherein each of the charge trapping structures (120) further includes second insulating films (123a, 123b) between the first charge trapping layer (122a) and the conductive film (125) and between the second charge trapping layer (122b) and the conductive film (125), respectively.
  10. The semiconductor device of any one of claims 1 to 9, wherein the at least one charge trapping layer (122) is in contact with the first insulating films (121).
  11. The semiconductor device of claim 10, wherein a width of the at least one charge trapping layer (122) in the first direction (X) is greater than widths of each of the first insulating films (121) in the first direction (X), respectively.
  12. The semiconductor device of any one of claims 1 to 11, wherein each of the word line structures (150) includes: a gate insulating pattern (151) between the bit line structure (110) and the first word line (152a) and the second word line (152b); first gate capping patterns (162) on an upper surface of the first word line (152a) and an upper surface of the second word line (152b); and a second gate capping pattern (164) arranged on the gate insulating pattern, arranged between the first word line (152a) and the second word line (152b), and arranged between the first gate capping patterns, wherein an upper surface of the charge trapping structure (120) is coplanar with upper surfaces of the first gate capping patterns (162) and an upper surface of the second gate capping pattern (164).
  13. The semiconductor device of any one of claims 1 to 12, further comprising contact insulating patterns between the contact patterns (170), wherein the contact insulation patterns (175) overlap the charge trapping structure (120) in a second direction (Z), intersecting the first direction (X).
  14. The semiconductor device of any one of claims 1 to 13, wherein the active patterns (140) include first to third active patterns (141, 142, 143) that are arranged in sequence in the first direction (X) on the bit line structure (110), wherein one of the charge trapping structures (120) is arranged between the first active pattern (141) and the second active pattern (142), wherein one of the word line structures (150) is arranged between the second active pattern (142) and the third active pattern (143), wherein the first word line (152a) opposing one side of the second active pattern (142), wherein the second word line (152b) opposing one side of the third active pattern (143) and spaced apart from the first word line (152a) in the first direction (X), and wherein the first insulating films (121) includes a first insulating pattern (121a) having a first side surface in contact with the first active pattern (141) and a second side surface opposing the first side surface and including a first insulating material and a second insulating pattern (121b) having a third side surface in contact with the second active pattern (142) and a fourth side surface opposing the third side surface and including the first insulating material.
  15. The semiconductor device of claim 14, wherein the at least one charge trapping layer (122) includes a first charge trapping layer (122a) in contact with the second side surface of the first insulating pattern and a second charge trapping layer (122b) in contact with the fourth side surface of the second insulating pattern, and wherein the one of the charge trapping structures further includes a third insulating pattern including the first insulating material between the first charge trapping layer (122a) and the second charge trapping layer (122b).

Description

BACKGROUND The present disclosure relates to semiconductor devices, and more particularly to semiconductor devices including a vertical channel transistor. As demand for high performance, high speed, and/or multifunctionality of semiconductor devices increases, the degree of integration of a semiconductor device has increased. In manufacturing fine-patterned semiconductor devices in response to the trend for high integration of semiconductor devices, it may be required to implement patterns having a fine width or a fine separation distance. US 2023/055499 discloses a DRAM memory device with vertical channels of the access transistors. US 2005/247982 discloses a planar DRAM device having access transistors with charge trapping regions. SUMMARY An aspect of the present disclosure is to provide a semiconductor device including a vertical channel transistor configured to increase integration density. However, objects of the present disclosure are not limited to the above-described objects, and may be variously extended. The invention is set out in the appended claims. The at least one charge trapping layer may function as a back gate capable of controlling charges accumulated in a vertical channel region of an active pattern. For example, the vertical channel region within the active pattern may be a floating body disposed between an upper source/drain region and a lower source/drain region, and the at least one charge trapping layer may suppress or prevent the performance of a transistor from being degraded due to a floating body effect. For example, the at least one charge trapping layer may minimize or prevent a change in a threshold voltage of the transistor by accumulating charges, i.e., holes, within the floating body in the vertical channel region. Advantages and effects of the embodiments disclosed herein are not limited to the foregoing content and may be variously extended. BRIEF DESCRIPTION OF THE DRAWINGS The above and other aspects, features, and advantages of the present disclosure will be more clearly understood from the following detailed description, taken in conjunction with the accompanying drawings, in which: FIG. 1 is a schematic perspective view of a semiconductor device according to an example embodiment of the present disclosure;FIG. 2 is a plan view of a semiconductor device according to an example embodiment of the present disclosure;FIG. 3 is a cross-sectional view taken along line I-I' of the semiconductor device illustrated in FIG. 2 according to an example embodiment;FIG. 4A is an enlarged view of region A of the semiconductor device of FIG. 3 according to an example embodiment;FIG. 4B is an enlarged view of region A of the semiconductor device of FIG. 3 according to another example embodiment;FIG. 4C is an enlarged view of region A of the semiconductor device of FIG. 3 according to another example embodiment;FIG. 5A is a view illustrating an operation of trapping a charge in a charge trapping layer of a charge trapping structure of the semiconductor device of FIG. 4A;FIG. 5B is a diagram illustrating an operation of trapping a charge in a charge trapping layer of a charge trapping structure of the semiconductor device of FIG. 4C; andFIGS. 6A to 6I are diagrams illustrating an example embodiment of a method of manufacturing a semiconductor device. DETAILED DESCRIPTION Hereinafter, example embodiments of the present disclosure will be described in more detail with reference to the attached drawings. The same reference numerals are used for the same components in the drawings, and duplicate descriptions for the same components are omitted. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "on," "attached" to, "connected" to, "coupled" with, "contacting," etc., another element, it can be directly on, attached to, connected to, coupled with or contacting the other element or intervening elements may also be present. In contrast, when an element is referred to as being, for example, "directly on," "directly attached" to, "directly connected" to, "directly coupled" with or "directly contacting" another element, there are no intervening elements present. In embodiments of the inventive concept, a singular form of the constituent components may include a plural form unless the context clearly indicates otherwise. In the present specification, the drawings are exaggerated for clarifying embodiments of the inventive concept. It is noted that aspects described with respect to one embodiment may be incorporated in different embodiments although not specifically described relative thereto. That is, all embodiments and/or features of any embodiments can be combined in any way and/or combination. FIG. 1 is a schematic perspective view of a semiconductor device according to an example embodiment of the present disclosure. Referring to FIG. 1, a semiconductor device 10