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EP-4677650-B1 - TRANSISTORS HAVING DIFFERENT CHANNEL LENGTHS AND COMPARABLE SOURCE/DRAIN SPACES

EP4677650B1EP 4677650 B1EP4677650 B1EP 4677650B1EP-4677650-B1

Inventors

  • LIM, Kwanyong
  • PARK, HYUNWOO
  • BAO, JUNJING
  • YANG, HAINING

Dates

Publication Date
20260513
Application Date
20240216

Claims (15)

  1. A semiconductor structure (300A), comprising: a first gate structure (330a) disposed on a substrate and having a first channel length (CLa) along a first direction; a second gate structure (330b) disposed on the substrate and having the first channel length along the first direction, a first source/drain space between the first gate structure and the second gate structure having a first distance (SC 1 ) along the first direction; a third gate structure (330c) disposed on the substrate and having a second channel length (CLc) along the first direction; and a fourth gate structure (330d) disposed on the substrate and having the second channel length along the first direction, a second source/drain space between the third gate structure and the fourth gate structure having a second distance (SC2 2 ) along the first direction, wherein the second channel length is different from the first channel length, and the second distance ranges from 0.75 times to 1.25 times the first distance.
  2. The semiconductor structure of claim 1, wherein: the first channel length is equal to or less than 20 nanometers, nm, and the second channel length is equal to or greater than 30 nm.
  3. The semiconductor structure of claim 1, wherein: a difference between the first distance and the second distance is less than 5 nanometers, nm.
  4. The semiconductor structure of claim 1, further comprising: a first channel structure; a second channel structure; a first source/drain structure disposed between the first gate structure and the second gate structure, the first source/drain structure coupling to the first channel structure and the second channel structure; a third channel structure; a fourth channel structure; and a second source/drain structure disposed between the third gate structure and the fourth gate structure, the second source/drain structure coupling to the third channel structure and the fourth channel structure; and further comprising: a first bottom dielectric structure between the first source/drain structure and the substrate, and a second bottom dielectric structure between the second source/drain structure and the substrate.
  5. The semiconductor structure of claim 1, wherein the semiconductor structure comprises a gate-all-around structure; or wherein the semiconductor structure comprises a FinFET structure.
  6. A method (700) of manufacturing a semiconductor structure, comprising: forming (710) a first gate structure disposed on a substrate and having a first channel length along a first direction; forming (720) a second gate structure disposed on the substrate and having the first channel length along the first direction, a first source/drain space between the first gate structure and the second gate structure having a first distance along the first direction; forming (730) a third gate structure disposed on the substrate and having a second channel length along the first direction; and forming (740) a fourth gate structure disposed on the substrate and having the second channel length along the first direction, a second source/drain space between the third gate structure and the fourth gate structure having a second distance along the first direction, wherein the second channel length is different from the first channel length, and the second distance ranges from 0.75 times to 1.25 times the first distance.
  7. The method of claim 6, wherein: the first channel length is equal to or less than 20 nanometers, nm, and the second channel length is equal to or greater than 30 nm; and wherein: a difference between the first distance and the second distance is less than 5 nanometers, nm.
  8. The method of claim 6, further comprising: forming a plurality of mask patterns on an intermediate structure, the plurality of mask patterns including a first mask pattern, a second mask pattern, a third mask pattern, and a fourth mask pattern, wherein the intermediate structure includes: a stack of one or more gate/channel material layers on the substrate, and one or more hardmask layers on the stack; forming a capping film covering the third mask pattern and the fourth mask pattern without covering the first mask pattern and the second mask pattern, the capping film constituting spacers on sidewalls of the third mask pattern and the fourth mask pattern; patterning the one or more hardmask layers and the stack to become: a first slab on the substrate based on the first mask pattern, a second slab on the substrate based on the second mask pattern, a third slab on the substrate based on the third mask pattern and the corresponding spacers on the sidewalls of the third mask pattern, and a fourth slab on the substrate based on the fourth mask pattern and the corresponding spacers on the sidewalls of the fourth mask pattern; and forming the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure based on the first slab, the second slab, the third slab, and the fourth slab, respectively.
  9. The method of claim 8, further comprising: forming a first source/drain structure between the first gate structure and the second gate structure, the first source/drain structure coupling to a first channel structure and a second channel structure; and forming a second source/drain structure between the third gate structure and the fourth gate structure, the second source/drain structure coupling to a third channel structure and a fourth channel structure.
  10. The method of claim 6, wherein the semiconductor structure comprises a gate-all-around structure; or wherein the semiconductor structure comprises a FinFET structure.
  11. The method of claim 9, further comprising: forming a first bottom dielectric structure prior to the forming the first source/drain structure, the first bottom dielectric structure being between the first source/drain structure and the substrate; and forming a second bottom dielectric structure prior to the forming the second source/drain structure, the second bottom dielectric structure being between the second source/drain structure and the substrate; or wherein the forming the first source/drain structure and the forming the second source/drain structure comprises: epitaxially growing the first source/drain structure and the second source/drain structure.
  12. The method of claim 8, wherein the forming the capping film comprises: forming a layer of capping film material on the plurality of mask patterns; and removing a portion of the layer of capping film material that covers the first mask pattern and the second mask pattern.
  13. The method of claim 12, wherein the layer of capping film material includes SiO 2 ; or wherein the removing the portion of the layer of capping film material comprises: forming a block pattern over the third mask pattern and the fourth mask pattern without covering the first mask pattern and the second mask pattern; and performing a wet etching process using the block pattern as a mask to remove the portion of the layer of capping film material.
  14. The method of claim 8, wherein: the one or more hardmask layers includes a first hardmask layer over a second hardmask layer, and the patterning the one or more hardmask layers and the stack comprises: patterning the first hardmask layer to become: a first hardmask pattern based on the first mask pattern, a second hardmask pattern based on the second mask pattern, a third hardmask pattern based on the third mask pattern and the corresponding spacers on the sidewalls of the third mask pattern, and a fourth hardmask pattern based on the fourth mask pattern and the corresponding spacers on the sidewalls of the fourth mask pattern; and patterning the second hardmask layer and the stack to become: the first slab based on the first hardmask pattern, the second slab based on the second hardmask pattern, the third slab based on the third hardmask pattern, and the fourth slab based on the fourth hardmask pattern.
  15. The method of claim 14, wherein: the first hardmask layer includes amorphous silicon, SiO 2 , amorphous carbon, or a combination thereof, and the second hardmask layer includes SiN; or wherein the patterning the first hardmask layer comprises: performing a dry etching process using the first mask pattern, the second mask pattern, the third mask pattern and the corresponding spacers on the sidewalls of the third mask pattern, and the fourth mask pattern and the corresponding spacers on the sidewalls of the fourth mask pattern as masks; or wherein the patterning the second hardmask layer and the stack comprises: performing a dry etching process using the first hardmask pattern, the second hardmask pattern, the third hardmask pattern, and the fourth hardmask pattern as masks.

Description

TECHNICAL FIELD The present disclosure generally relates to semiconductor structures, and more particularly, to a semiconductor structure that includes multiple transistors having different channel lengths and comparable source/drain spaces. BACKGROUND Integrated circuit (IC) technology has achieved great strides in advancing computing capabilities through miniaturization and modification of semiconductor components such as transistors. For example, the progression of the transistors has progressed from bulk substrates and planar metal-oxide-semiconductor field-effect transistors (MOSFETs), to three-dimensional stacking transistors such as fin field-effect transistors (FinFETs) or gate-all-around (GAA) transistors (e.g., nanowire field-effect transistors (FETs) or nanosheet FETs). Also, the technology nodes of semiconductor manufacturing processes have evolved from 14 nanometers (nm), 10 nm, 7 nm, to 3 nm and beyond. To form various elements of the semiconductor components at the reduced sizes, advanced lithographic processes are introduced with enhanced spatial resolutions. However, due to diffraction and/or other optical effects or interferences, even for a same lithographic process, patterns with different sizes and/or spaces may be subject to different design rules. Accordingly, the minimum spaces between patterns formed using a lithographic process may vary based on the sizes of the patterns US 2022/310602 A1 discloses a semiconductor structure comprising several transistors on a substrate, as known from the prior art. Therefore, there is a need for an improved manufacturing process for forming a space between two elements that is smaller than the minimum space allowable by the design rules of a particular lithographic process, in order to further reduce the size of the semiconductor components and/or achieve improved characteristics in the manufacturing process (e.g., an improved IC performance, a new or improved element or component configuration, a higher yield rate, a higher throughput, etc.). SUMMARY The following presents a simplified summary relating to one or more aspects disclosed herein. Thus, the following summary should not be considered an extensive overview relating to all contemplated aspects, nor should the following summary be considered to identify key or critical elements relating to all contemplated aspects or to delineate the scope associated with any particular aspect. Accordingly, the following summary has the sole purpose to present certain concepts relating to one or more aspects relating to the mechanisms disclosed herein in a simplified form to precede the detailed description presented below. In an aspect, a semiconductor structure includes a first gate structure disposed on a substrate and having a first channel length along a first direction; a second gate structure disposed on the substrate and having the first channel length along the first direction, a first source/drain space between the first gate structure and the second gate structure having a first distance along the first direction; a third gate structure disposed on the substrate and having a second channel length along the first direction; and a fourth gate structure disposed on the substrate and having the second channel length along the first direction, a second source/drain space between the third gate structure and the fourth gate structure having a second distance along the first direction, wherein the second channel length is different from the first channel length, and the second distance ranges from 0.75 times to 1.25 times the first distance. In an aspect, a method of manufacturing a semiconductor structure includes forming a first gate structure disposed on a substrate and having a first channel length along a first direction; forming a second gate structure disposed on the substrate and having the first channel length along the first direction, a first source/drain space between the first gate structure and the second gate structure having a first distance along the first direction; forming a third gate structure disposed on the substrate and having a second channel length along the first direction; and forming a fourth gate structure disposed on the substrate and having the second channel length along the first direction, a second source/drain space between the third gate structure and the fourth gate structure having a second distance along the first direction, wherein the second channel length is different from the first channel length, and the second distance ranges from 0.75 times to 1.25 times the first distance. Other objects and advantages associated with the aspects disclosed herein will be apparent to those skilled in the art based on the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings are presented to aid in the description of various aspects of the disclosure and are provided solely for illustration of the aspects and not limitati