INTEGRATED CIRCUIT STRUCTURES HAVING METAL-CONTAINING FIN ISOLATION REGIONS

Abstract

Integrated circuit structures having metal-containing fin isolation regions are described. In an example, an integrated circuit structure comprises: a set of nanowires over a first sub-fin; a gate stack surrounding each of the nanowires of the set of nanowires, the gate stack comprising a gate dielectric and a gate electrode, the gate dielectric in contact with each of the nanowires of the set of nanowires; a fin-trim isolation structure over a second sub-fin; a trench isolation structure along sides of the first sub-fin and the second sub-fin; and a dielectric gate cut plug laterally between the gate stack and the fin-trim isolation structure, the dielectric gate cut plug in contact with the fin-trim isolation structure, the dielectric gate cut plug in contact with the gate electrode of the gate stack, and the dielectric gate cut plug extending into the trench isolation structure between the first sub-fin and the second sub-fin.

Inventors

GULER, Leonard
CHANDHOK, MANISH
CHANG, Tsuan-Chung
JOACHIM, ROBERT
NGUYEN, PETER
MAO, Lily
SKIBINSKI, Erik

Assignees

INTEL Corporation

Dates

Publication Date: 20260513
Application Date: 20231030