INTEGRATED CIRCUIT STRUCTURES HAVING FIN ISOLATION REGIONS RECESSED FOR GATE CONTACT

Abstract

Integrated circuit structures having fin isolation regions recessed for gate contact are described. In an example, an integrated circuit structure comprises: a first set of nanowires over a first sub-fin; a first gate stack surrounding each of the nanowires of the first set of nanowires, the first gate stack including a first gate dielectric and a first gate electrode, the first gate stack having a first side laterally opposite a second side; a first gate insulating cap layer on the first gate electrode of the first gate stack; a second set of nanowires over a second sub-fin, the second set of nanowires laterally spaced apart from the first side of the first gate stack; a second gate stack surrounding each of the nanowires of the second set of nanowires, the second gate stack including a second gate dielectric and a second gate electrode; a second gate insulating cap layer on the second gate electrode of the second gate stack; a dielectric gate cut plug laterally between the first set of nanowires and the second set of nanowires, the dielectric gate cut plug in contact with the first gate electrode of the first gate stack, the dielectric gate cut plug in contact with the second gate electrode of the second gate stack; a fin trim isolation structure over a third sub-fin, the fin trim isolation structure at the second side of the first gate stack; and an interconnect in the first gate insulating cap layer and coupled to the first gate electrode of the first gate stack.

Inventors

GULER, Leonard P.
ONG, Clifford
YEMENICIOGLU, SUKRU
GHANI, TAHIR

Assignees

INTEL Corporation

Dates

Publication Date: 20260506
Application Date: 20230712