EP-4735205-A1 - DOUBLE-SIDED POLISHING OF SEMICONDUCTOR WAFERS WITH DYNAMIC CONTROL

EP4735205A1EP 4735205 A1EP4735205 A1EP 4735205A1EP-4735205-A1

Abstract

A polishing apparatus and method for double-sided polishing of semiconductor wafers including a first platen, a second platen, a wafer carrier, and a controller is disclosed. The controller operable to perform operations including determining whether a batch of the semiconductor wafers is loaded on the wafer carrier for double-sided polishing and retrieving specification for the batch of semiconductor wafers. The operations include determining an amount of tuning required for one or more flatness control parameters and based on the amount of tuning required for the one or more flatness control parameters, identifying or generating a recipe to perform the double-sided polishing on the batch of the semiconductor wafers. Operations may include storing statistical process control (SPC) feedback data in a database to perform one or more additional iterations of the double-sided polishing on the batch of the semiconductor wafers.

Inventors

CHU, YUNG HSING
YANG, Yau-Ching
LIN, TSUNG CHIEH
LI, MENG HUNG
CHEN, LIANG CHIN

Assignees

Globalwafers Co., Ltd.

Dates

Publication Date: 20260506
Application Date: 20240625

Claims (20)

1. A polishing apparatus for double-sided polishing of semiconductor wafers, the polishing apparatus comprising: a first platen; a second platen; a wafer carrier disposed within a gap formed between the first platen and the second platen; and a controller configured to perform operations comprising: determining whether a batch of the semiconductor wafers is loaded on the wafer carrier for double-sided polishing; in accordance with the determining that the batch of semiconductor wafer is loaded, retrieving specification for the batch of semiconductor wafers; based on the retrieved specification for the batch of semiconductor wafers, determining an amount of tuning required for one or more flatness control parameters; based on the amount of tuning required for the one or more flatness control parameters, identifying, or generating a recipe to perform the double-sided polishing on the batch of the semiconductor wafers; and upon performing the double-sided polishing on the batch of the semiconductor wafers according to the identified recipe, storing statistical process control (SPC) feedback data in a database to perform one or more additional iterations of the double-sided polishing on the batch of the semiconductor wafers.
2. The polishing apparatus of claim 2, wherein retrieving specification for the batch of semiconductor wafers comprises retrieving at least one of: incoming specification for the batch of semiconductor wafers, current specification for the batch of semiconductor wafers, or target specification for the batch of semiconductor wafers.
3. The polishing apparatus of claim 1, wherein the one or more flatness control parameters include at least one of: edge roll-off, or doming.
4. The polishing apparatus of claim 1, wherein the identifying or generating the recipe comprises: based on the retrieved specification for the batch of semiconductor wafers, identifying a set of double-sided polishing parameters for tuning and a respective value for each parameter of the set of double-sided polishing parameters to perform an iteration of the double-sided polishing on the batch of semiconductor wafers; making predictions of a respective value of each of the one or more flatness control parameters based on identified set of double-sided polishing parameters for tuning and the respective value for each parameter of the set of double-sided polishing parameters; based on the predictions of the respective value of each of the one or more flatness control parameters, identifying or generating the recipe corresponding to the identified set of double-sided polishing parameters for tuning and the respective values for each parameter.
5. The polishing apparatus of claim 4, wherein the identifying or generating the recipe further comprises determining whether the set of double-sided polishing parameters for tuning and the respective value for each parameter of the set of double-sided polishing parameters are available for performing the double-sided polishing on the batch of the semiconductor wafers.
6. The polishing apparatus of claim 4, wherein the set of doublesided polishing parameters for tuning includes at least one of: thickness or step time.
7. The polishing apparatus of claim 4, wherein the set of doublesided polishing parameters for tuning includes at least one of: a top platen profile or a bottom platen profile.
8. The polishing apparatus of claim 4, wherein the set of doublesided polishing parameters for tuning includes at least one of: a rotational speed of a top platen, a rotational speed of bottom platen, a number of inner pin gears, or a number of outer pin gears.
9. The polishing apparatus of claim 4, wherein making the predictions of the respective value of each of the one or more flatness control parameters comprises making predictions using one or more algorithms configured to predict the respective value of each of the one or more flatness control parameters based on historical SPC feedback data.
10. The polishing apparatus of claim 1 , wherein the SPC feedback data includes incoming specification for the batch of semiconductor wafers, current specification for the batch of semiconductor wafers, or target specification for the batch of semiconductor wafers, a batch run number, information of a customer, information of a customer order, or batch ID of the semiconductor wafers.
1 1. A control system operatively connected with a polishing apparatus for double-sided polishing of semiconductor wafers, the control system comprising: at least one memory configured to store instructions; and at least one processor configured to execute the stored instructions, which when executed, cause the at least one processor to perform operations comprising: determining whether a batch of the semiconductor wafers is loaded on a wafer carrier of the polishing apparatus; in accordance with the determining that the batch of semiconductor wafer is loaded, retrieving specification for the batch of semiconductor wafers; based on the retrieved specification for the batch of semiconductor wafers, determining an amount of tuning required for one or more flatness control parameters; based on the amount of tuning required for the one or more flatness control parameters, identifying, or generating a recipe to perform the double-sided polishing on the batch of the semiconductor wafers; causing the polishing apparatus to perform double-sided polishing on the batch of semiconductor wafers using the recipe; and receiving and storing statistical process control (SPC) feedback data in a database to perform one or more additional iterations of the doublesided polishing on the batch of the semiconductor wafers.
12. The control system of claim 11, wherein retrieving specification for the batch of semiconductor wafers comprises retrieving at least one of: incoming specification for the batch of semiconductor wafers, current specification for the batch of semiconductor wafers, or target specification for the batch of semiconductor wafers.
13. The control system of claim 11, wherein the one or more flatness control parameters include at least one of: edge roll-off, or doming.
14. The control system of claim 11, wherein the identifying or generating the recipe comprises: based on the retrieved specification for the batch of semiconductor wafers, identifying a set of double-sided polishing parameters for tuning and a respective value for each parameter of the set of double-sided polishing parameters to perform an iteration of the double-sided polishing on the batch of semiconductor wafers; making predictions of a respective value of each of the one or more flatness control parameters based on identified set of double-sided polishing parameters for tuning and the respective value for each parameter of the set of double-sided polishing parameters; based on the predictions of the respective value of each of the one or more flatness control parameters, identifying or generating the recipe corresponding to the identified set of double-sided polishing parameters for tuning and the respective values for each parameter.
15. The control system of claim 14. wherein the identifying or generating the recipe further comprises determining whether the set of double-sided polishing parameters for tuning and the respective value for each parameter of the set of double-sided polishing parameters are available for performing the double-sided polishing on the batch of the semiconductor wafers.
16. The control system of claim 14, wherein the set of double-sided polishing parameters for tuning includes at least one of thickness, step time, a top platen profile, a bottom platen profile, a rotational speed of a top platen, a rotational speed of bottom platen, a number of inner pin gears, or a number of outer pin gears.
17. The control system of claim 14, wherein making the predictions of the respective value of each of the one or more flatness control parameters comprises making predictions using one or more algorithms configured to predict the respective value of each of the one or more flatness control parameters based on historical SPC feedback data.
18. The control system of claim 17, wherein the one or more algorithms are machine-learning algorithms trained using the historical SPC feedback data.
19. The control system of claim 1 1, wherein the SPC feedback data includes incoming specification for the batch of semiconductor wafers, current specification for the batch of semiconductor wafers, or target specification for the batch of semiconductor wafers, a batch run number, information of a customer, information of a customer order, or batch ID of the semiconductor wafers.
20. A method, comprising: determining whether a batch of the semiconductor wafers is loaded on a wafer earner of a double-sided polishing apparatus; in accordance with the determining whether the batch of semiconductor wafer is loaded, retrieving specification for the batch of semiconductor wafers; based on the retrieved specification for the batch of semiconductor wafers, determining an amount of tuning required for one or more flatness control parameters; based on the amount of tuning required for the one or more flatness control parameters, identifying a recipe to perform double-sided polishing on the batch of the semiconductor wafers, the recipe being identified based on analysis of historical statistical process control (SPC) feedback data; and upon performing an iteration of the double-sided polishing on the batch of the semiconductor wafers according to the recipe, storing SPC feedback data corresponding to the performed iteration in a database.

Description

DOUBLE-SIDED POLISHING OF SEMICONDUCTOR WAFERS WITH DYNAMIC CONTROL CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application claims priority to U.S. Patent Application No. 18/342,172, filed on 27 June 2023, the disclosure of which is incorporated by reference in its entirety7. FIELD [0002] This disclosure relates to polishing of semiconductor wafers and more particularly to systems and methods for double-sided polishing of semiconductor wafers using dynamic control. BACKGROUND [0003] Semiconductor wafers are commonly used in the production of integrated circuit (IC) chips on which circuitry is printed. The circuitry is first printed in miniaturized form onto surfaces of the wafers. The wafers are then broken into circuit chips. This miniaturized circuitry7 requires that front and back surfaces of the wafer be extremely flat and parallel to ensure that the circuitry can be properly printed over the entire surface of the wafer. Flatness of the wafer surface on which circuits are to be printed is critical in order to maintain resolution of the lines, which can be as thin as 0.13 microns (5.1 microinches) or less. The need for a flat wafer surface, and in particular local flatness in discrete areas on the surface, is heightened when stepper lithographic processing, such as an electron beam-lithographic or photolithographic process (hereinafter '‘lithography’’), is employed. To accomplish this, grinding and polishing processes are commonly used to improve flatness and parallelism of the front and back surfaces of the wafer after the wafer is cut from an ingot. [0004] A particularly good finish is required when polishing the wafer in preparation for printing the miniaturized circuits on the wafer by lithography. The wafer surface on which the miniaturized circuits are to be printed must be flat. Typically, flatness of the polished surfaces of the wafer are acceptable when a new polishing pad is used on the wafer, but the flatness becomes unacceptable as the polishing pad wears down over the course of polishing many wafers. [0005] The construction and operation of conventional polishing machines contribute to the unacceptable flatness parameters. Polishing machines typically include a circular or annular polishing pad mounted on a turntable or platen for driven rotation about a vertical axis passing through the center of the pad. A polishing slurry, ty pically including chemical polishing agents and abrasive particles, is applied to the pad for greater polishing interaction between the polishing pad and the surface of the wafer. This type of polishing operation is typically referred to as chemical-mechanical polishing or simply CMP. [0006] During operation, the pad is rotated, and the wafer is brought into contact with the pad. As the pad wears, e.g., after a few hundred wafers, wafer flatness parameters degrade because the pad is no longer flat, but instead has a worn annular band forming a depression along the polishing surface of the pad. Such pad wear impacts wafer flatness and may cause "dishing" or '‘doming.” [0007] As illustrated in FIG. 1, “doming,” results in the wafer 50 having a generally convex polished surface 52. The convex surface 52 may be caused by a worn pad removing less material from the center of the front surface of the wafer 50 than from the areas closer to the wafer's edge 54. This is because the worn pad's removal rate is inverse to its wear. In other words, the portions of the worn pad with less wear remove more material than portions of the worn pad with more wear. The least amount of material is removed from the wafer 50 by the portion of the pad corresponding to the worn annular band. As a result, the polished surface 52 of the wafer is caused to have a generally “domed” shaped. [0008] As illustrated in FIG. 2, "dishing" results in the wafer 60 having a generally concave polished surface 62. One potential reason for this occurring is that the polishing pad becomes embedded with abrasives (e.g., colloidal material from the slurry, debris from previously polished wafers, and debris from a retaining ring) causing the removal rate to increase in the areas of w ear. The portions of the pad with more wear remove more material from the wafer during the polishing process than portions of the pad with less wear. As a result, more material to be removed from the center of the wafer 60 than from its edge 64 resulting in the polished surface 62 of the wafer having a generally "‘dished” shape. [0009] In addition, due to an uneven distribution of mechanical and/or chemical forces near an edge of the wafer, a thickness profile at the peripheral edge of the wafer may be reduced, which is known as edge roll-off. Edge roll-off reduces the useful portion of the wafer available for device fabrication. Edge roll-off is generally controlled by adjusting an amount of slurry and/or a type of slurry applied to the pads. [0010] When the flatness of the wafers becomes unacceptable (e.g., too “domed” o