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EP-4735661-A1 - INHERENT AREA SELECTIVE DEPOSITION OF SILICON-CONTAINING DIELECTRIC ON METAL SUBSTRATE

EP4735661A1EP 4735661 A1EP4735661 A1EP 4735661A1EP-4735661-A1

Abstract

An inherently selective process for the deposition of silicon-containing dielectric layers on metal layers includes atomic layer deposition or chemical vapor deposition utilizing a chemical precursor comprising silicon and sulfur, and an oxidant. An optional buffer layer may be present between the metal layer and the selectively deposited film.

Inventors

  • BRICK, Chad, Michael
  • OGATA, TOMOYUKI

Assignees

  • GELEST, INC.

Dates

Publication Date
20260506
Application Date
20240801

Claims (20)

  1. 1. A method for selectively depositing a silicon-containing dielectric layer upon a patterned substrate, the method comprising: (a) introducing a patterned substrate into a reaction zone of a deposition chamber, the patterned substrate comprising at least one metallic region and at least one isolated non-metallic region, where a temperature of the reaction zone is between about 25 °C and about 500°C; and (b) forming a silicon-containing dielectric layer overlaying only the at least one metallic region of the patterned substrate via an atomic layer deposition process or a chemical vapor deposition process, wherein the patterned substrate is exposed to a compound comprising silicon and sulfur, and wherein the patterned substrate is exposed to an oxidant.
  2. 2. The method according to claim 1, wherein the silicon-containing dielectric layer forms upon the at least one metallic region of the patterned substrate at a thickness of at least about two nanometers and does not form upon the at least one non-metallic region of the patterned substrate or forms upon the at least one non-metallic region of the patterned substrate at a thickness of less than about one nanometer.
  3. 3. The method according to claim 1 or 2, wherein the compound comprising silicon and sulfur comprises at least one direct silicon-sulfur bond or a silicon and sulfur atom connected by a linear, branched, or cyclic, optionally substituted, alkylene, aryl, alkyne, alkene, ether, ester, or ketone having 1 to about 12 carbon atoms.
  4. 4. The method according to any of claims 1-3, wherein the silicon and sulfur containing compound has Formula 1, Formula 2, Formula 3, Formula 4, Formula 5, Formula 6, Formula 7, or Formula 8: Formula 1 Formula 2 Formula 3 Formula 4 Formula 5 Formula 6 Formula 7 Formula 8 wherein n is an integer from about 1 to 4, m is an integer from about 1 to 6, Ri, R2, R3, R4, Rs. Re. and R7 are each independently hydrogen or a linear, branched, or cyclic, optionally substituted, alkoxy, alkyl, aryl, alkyne, alkene, ether, ester, ketone, alkylthio, (alkyl)amino, (dialkyl)amino, alkyl(alkylamino), or alkyl(dialkylamino) group having 1 to about 12 carbon atoms; or a linear, branched, or cyclic, optionally substituted, silyl group having general formula SiRnRuRis, OSiRuRuRis, or RieSiRi iRuRis wherein R13, R14, and R15 are each independently hydrogen or an alkyl or alkoxy group having about 1 to about 12 carbon atoms; and Ri6 an linear or branched alkyl group having 1 to about 12 carbon atoms; Rs is hydrogen or a linear, branched, or cyclic, optionally substituted, alkyl, aryl, alkyne, alkene, ether, ester, ketone, alkylthio, (alkyl)amino, (dialkyl)amino, alkyl(alkylamino), or alkyl(dialkylamino) group having 1 to about 12 carbon atoms; or a linear, branched, or cyclic, optionally substituted, silyl group having general formula SiRnRuRis, or RisSiRi iRuRis; R9, Rio and Rn are each independently a linear, branched, or cyclic, optionally substituted, alkylene, aryl, alkyne, alkene, ether, ester, or ketone having 1 to about 12 carbon atoms; R12 is OH, Cl, NR17R18, aryl or CN, wherein R17 and Ris are each independently hydrogen or a linear, branched, or cyclic, optionally substituted, alkyl, aryl, alkyne, alkene, ether, ester, or ketone having 1 to about 12 carbon atoms; and X = Si(R 3 ,R4)-(S- Si(R5,Re)) P or (CH2) q , wherein p is an integer from 0 to about 3 and q is an integer from about 1 to 4.
  5. 5. The method according to claim 4, wherein the compound of Formula 1, Formula 2, Formula 3, Formula 4, Formula 5, Formula 6, Formula 7, or Formula 8 is 2,2,4-trimethyl-l-thia- 2-silacyclopentane, 2,2-dimethoxy-l-thia-2-silacyclopentane, 2,2-diethoxy-l-thia-2- silacyclopentane, bis(trimethylsilyl) sulfide, (mercaptomethyl)methyldiethoxysilane, tri methyl si lan ethiol, 2,2-methyl-l-thia-2-silacyclopentane, 2,2-dimethoxy-4-methyl-l -thia-2- silacyclopentane, 2,2-diethoxy-4-methyl-l-thia-2-silacyclopentane, silanethiol, triisopropylsilanethiol, trimethoxysilanethiol, triethoxysilanethiol, disilathiane, trimethyl (methylthio)silane, trimethyl(ethylthio)silane, 2,2-dimethyl-l,3-dithia-2- silacyclopentane, 2,2,4,4-tetramethylcyclodisilathiane, 2,2,8,8-tetramethyl-3,7-dithia-2,8- disilanonane, hexamethylcyclotrisilthiane, [(trimethylsilyl)thio]benzene, (3- mercaptopropyl)trimethoxysilane, [[(trimethylsilyl)thio]methyl]benzene, 2- (trimethylsilyl)ethanesulfonyl chloride, 2-(trimethylsilyl)ethanesulfonamide, (3- mercaptopropyl)triethoxysilane, 4-(dimethoxymethylsilyl)-l -butanethiol, 3-(trimethoxysilyl)-l- propanesulfonic acid, [[(trimethylsilyl)methyl]sulfonyl]benzene, bis[3-(triethoxysilyl)propyl] tetrasulfide, l,l’-thiobis(methylene)bis[ 1,1,1 -trimethylsilane], or 1- (di ethoxy m ethyl si ly l)m ethanethi ol .
  6. 6. The method according to claim 5, wherein the compound comprising silicon and sulfur is 2,2,4-trimethyl- 1 -thia-2-silacyclopentane, 2,2-dimethoxy- 1 -thia-2-silacy clopentane, (mercaptomethyl )methyldiethoxysilane, or 2, 2-di ethoxy- l-thia-2-silacy clopentane.
  7. 7. The method according to any of claims 1-6, wherein the patterned substrate is exposed to the compound comprising silicon and sulfur and to the oxidant simultaneously.
  8. 8. The method according to any of claims 1-6, wherein the patterned substrate is exposed to the compound comprising silicon and sulfur and to the oxidant sequentially.
  9. 9. The method according to any of claims 1-8, further comprising prior to step (b): performing an anneal, clean, etch, or plasma treatment on the patterned substrate.
  10. 10. The method according to any of claims 1-9, further comprising prior to step (b): exposing the patterned substrate to a chemical blocking agent to selectively passivate at least one region of the substrate.
  11. 11. The method according to any of claims 1-10, wherein the oxidant is a plasma generated from a gas mixture comprising at least one of O2, H2O, H2O2, O3, CO2, N2O, and NO2 and optionally a carrier gas comprising N2, Ar or He.
  12. 12. The method according to any of claims 1-11, wherein the silicon-containing dielectric layer has a thickness of about 2 nm to about 20 nm.
  13. 13. The method according to claim 12, wherein the silicon-containing dielectric layer has a thickness of about 3 nm to about 10 nm.
  14. 14. The method according to any of claims 1-13, wherein the temperature of the reaction chamber is about 75°C to about 300°C.
  15. 15. The method according to any of claims 1-14, wherein the patterned substrate comprises silicon dioxide, silicon oxycarbide, silicon oxynitride, silicon carboxynitride, silicon oxyfluoride, silicon nitride, silicon carbon nitride, silicon carbide borosilicate, carbon, or alumina.
  16. 16. The method according to any of claims 1-15, wherein the silicon-containing dielectric layer selectively grows on at least one area of the patterned substrate comprising copper, cobalt, ruthenium, molybdenum, tungsten, and/or gold.
  17. 17. The method according to any of claims 1-16, wherein the deposited fdm has a dielectric constant less than about 10.
  18. 18. The method according to claim 17, wherein the deposited film has a dielectric constant less than about 5.
  19. 19. The method according to any of claims 1-18, wherein an atomic layer deposition process is used to form the silicon-containing dielectric layer.
  20. 20. The method according to claim 19, wherein the atomic layer deposition process comprises: (bl) exposing the patterned substrate to a pulse of the compound comprising silicon and sulfur; (b2) optionally purging the deposition chamber; (b3) exposing the patterned substrate to the oxidant; (b4) optionally purging the deposition chamber; and (b5) repeating steps (bl) to (b4) until a desired layer thickness is reached.

Description

TITLE OF THE INVENTION [0001] Inherent Area Selective Deposition of Silicon-Containing Dielectric on Metal Substrate CROSS-REFERENCE TO RELATED APPLICATION [0002] This application claims priority to U.S. Provisional Patent Application No. 63/536,743, filed September 6, 2023, the disclosure of which is herein incorporated by reference in its entirety. BACKGROUND OF THE INVENTION [0003] In order to create functional semiconductor devices, it is often necessary to deposit insulating oxide layers on metal structures such as interconnects, gate electrodes, and contact pads. However, depositing oxide layers directly and selectively on metal surfaces in the presence of other oxide or nitride layers can be a challenging process due to the differences in reactivity and surface energies between the deposited material and target substrate and the similarity of the deposited material to the non-targeted surfaces. In particular, deposition of an oxide layer as a dielectric cap layer in recessed trenches has been proposed as a key target area for dielectric-on- metal (DoM) research, due to the difficulty of traditional photolithographic and etch processes to created well-formed, flat dielectric layers at the bottom of trenches. [0004] Current methods of depositing dielectrics on metals utilize photolithography to pattern dielectrics that have been deposited across the entire substrate. However, as feature sizes shrink, alignment errors of the photolithographic masks are becoming an ever-increasing source of device failure. Furthermore, photolithography is a complex process involving many individual process steps and associated costs. Area-Selective Deposition (ASD), which obviates the need for the photolithographic process by depositing desired materials only on targeted areas of the substrate, is an increasingly important area of the semiconductor fabrication process. Many ASD schemes have been published in recent years, but few involve the deposition of dielectrics selectively on metals with other and/or the same dielectric as the non-growth surface, due to the inherent difficulty in developing a chemistry for the deposition of oxide-based dielectrics that is selective to a metal surface with significantly different chemical and physical properties in preference to a dielectric surface with chemical and physical properties similar to the growing layer. Furthermore, to the extent that selective dielectric-on-metal schemes have been reported, many of the metal oxide dielectrics that were deposited, such as AI2O3, ZnO, Fe2O3, Ta2Os. or M 3O4. have high dielectric constants and thus are not suitable as the dielectric insulators that are required in most semiconductor applications. [0005] It has been found that the selective deposition of dielectrics with low dielectric constant on metals without simultaneous deposition of the dielectric on existing dielectric areas of the substrate presents several unique challenges, among them the chemical similarity of the growing dielectric fdm and the non-growth surface or surfaces, and the incompatibility of the harsh deposition processes used for dielectric deposition with the blocking layers typically used in ASD schemes. Existing reports of dielectric-on-metal deposition resolve these questions by depositing dielectric layers that have distinct chemistry relative to the existing dielectric layers of the fdm, which are typically comprised of silica, SiOC low-k dielectrics, silicon nitride, or other silicon-based fdms. In these reports, oxides such as alumina, zinc oxide, iron oxide, tantalum oxide, or manganese oxide have been deposited selectively on metal relative to dielectric surfaces. However, these oxides have high dielectric constants and limited practical utility. [0006] Several ASD processes for the selective deposition of dielectrics on metal substrates have been reported in the literature, such as in U.S. Patent No. 1 1,830,732; U.S. Patent No. 11,643,720; U.S. Patent No. 11,450,529; Oh et al. (Advanced Functional Materials (2024); Li et al., (Molecules, 26, 3056 (2021)); Cho et al., (Applied Surface Science, 622 (2023)); Chen et al. (Chem. Mater., 17, 536-544 (2005)); Lui et al., (Adv. Mater. Interfaces, 10 (2023)); and Singh et al., (Chem. Mater., 30, 663-670 (2018)). These disclosures are limited to high-k oxides such as alumina, hafnia, zirconia, and oxides of tantalum, iron, nickel, and manganese. Furthermore, few of these reports involve inherent selectivity but rather utilize complicated blocking/unblocking schemes to direct growth of a dielectric onto a target metal surface. While high-k oxides are suitable for some applications, low-k oxides comprising silicon are highly desirable in many applications and device structures. [0007] What is desired is a method for depositing a low dielectric constant fdm such as SiCL selectively on the metal areas of a substrate without concomitant deposition on pre-existing dielectric areas of the patterned semiconductor subst