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EP-4735826-A1 - CONCENTRICITY OFFSET MEASUREMENT FOR HYBRID BONDING

EP4735826A1EP 4735826 A1EP4735826 A1EP 4735826A1EP-4735826-A1

Abstract

A metrology system is used to measure a bonded wafer with a top wafer disposed on a carrier wafer. An imaging system generates wafer edge profile images of a circumferential edge of the bonded wafer. The wafer edge profile images can be converted to greyscale. An edge of the bonded wafer can be determined in each of the wafer edge profile images. The pixels in the wafer edge profile images can be converted to a grid and an offset can be determined between the top wafer and carrier wafer.

Inventors

  • BHATT, HEMANG ASHVINBHAI
  • VANGAL, ARAVINDH

Assignees

  • KLA Corporation

Dates

Publication Date
20260506
Application Date
20240911

Claims (16)

  1. 1. A metrology system comprising: a stage configured support a bonded wafer, wherein the bonded wafer has a top wafer disposed on a carrier wafer; and an imaging system configured to generate wafer edge profile images of a circumferential edge of the bonded wafer, wherein the imaging system includes a light source configured to generate collimated light and a detector configured to generate the wafer edge profile images; and a processor in electronic communication with the imaging system, wherein the processor is programmed to: receive the wafer edge profile images; convert the wafer edge profile images from black and white to greyscale; determine an edge of the bonded wafer in each of the wafer edge profile images based on bright pixels and dark pixels in the wafer edge profile images; convert pixels of the edge in the wafer edge profile images to a dimension scale in a grid; and determine an offset between the top wafer and the carrier wafer.
  2. 2. The metrology system of claim 1, wherein the wafer edge profile images received by the processor are shadowgram images.
  3. 3. The metrology system of claim 1 , wherein the processor is further configured to crop the wafer edge profile images prior to determining the boundary.
  4. 4. The metrology system of claim 1 , wherein the grid is a spreadsheet.
  5. 5. The metrology system of claim 1 , wherein the wafer edge profile images include from 20 to 30 of the wafer edge profile images for the bonded wafer.
  6. 6. A method comprising: receiving wafer edge profile images of a bonded wafer at a processor, wherein the bonded wafer has a top wafer disposed on a carrier wafer; converting the wafer edge profile images from black and white to greyscale using the processor; determining an edge of the bonded wafer in each of the wafer edge profile images using the processor based on bright pixels and dark pixels in the wafer edge profile images; converting pixels of the edge in the wafer edge profile images to a dimension scale in a grid using the processor; and determining an offset between the top wafer and the carrier wafer using the processor.
  7. 7. The method of claim 6, wherein the wafer edge profile images received by the processor are shadowgram images.
  8. 8. The method of claim 6, further comprising cropping the wafer edge profile images prior to determining the boundary.
  9. 9. The method of claim 6, wherein the grid is a spreadsheet.
  10. 10. The method of claim 6, wherein the wafer edge profile images include from 20 to 30 of the wafer edge profile images for the bonded wafer.
  11. 11. The method of claim 6, further comprising imaging a circumferential edge of the bonded wafer using an imaging system to generate the wafer edge profile images, wherein the imaging system includes a light source configured to generate collimated light and a detector configured to generate the wafer edge profile images.
  12. 12. A non-transitory computer-readable storage medium, comprising one or more programs for executing the following steps on one or more computing devices: receive wafer edge profile images of a bonded wafer, wherein the bonded wafer has a top wafer disposed on a carrier wafer; convert the wafer edge profile images from black and white to greyscale; determine an edge of the bonded wafer in each of the wafer edge profile images based on bright pixels and dark pixels in the wafer edge profile images; convert pixels of the edge in the wafer edge profile images to a dimension scale in a grid; and determine an offset between the top wafer and the carrier wafer.
  13. 13. The transitory computer-readable storage medium of claim 12, wherein the wafer edge profile images are shadowgram images.
  14. 14. The transitory' computer-readable storage medium of claim 12, wherein the steps fur ther include cropping the wafer edge profile images prior to determining the boundary.
  15. 15. The transitory computer-readable storage medium of claim 12, wherein the grid is a spreadsheet.
  16. 16. The transitory' computer-readable storage medium of claim 12, wherein the wafer edge profile images include from 20 to 30 of the wafer edge profile images for the bonded wafer.

Description

CONCENTRICITY OFFSET MEASUREMENT FOR HYBRID BONDING CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application claims priority to the provisional patent application filed September 12, 2023 and assigned U.S. App. No. 63/537,887, the disclosure of which is hereby incorporated by reference. FIELD OF THE DISCLOSURE [0002] This disclosure relates to bonded wafer metrology. BACKGROUND OF THE DISCLOSURE [0003] Evolution of the semiconductor manufacturing industry is placing greater demands on yield management and, in particular, on metrology and inspection systems. Critical dimensions continue to shrink, yet the industry needs to decrease time for achieving high-yield, high-value production. Minimizing the total time from detecting a yield problem to fixing it maximizes the return-on-investment for a semiconductor manufacturer. [0004] Fabricating semiconductor devices, such as logic and memory devices, typically includes processing a semiconductor wafer using a large number of fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a photoresist arranged on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing (CMP), etching, deposition, and ion implantation. An arrangement of multiple semiconductor devices fabricated on a single semiconductor wafer may be separated into individual semiconductor devices. [0005] Bonded (or stacked) wafers are frequently used in the semiconductor industry'. One or more ultrathin wafers bonded to a carrier wafer is an example of a bonded wafer, though other semiconductor wafer designs also can be bonded wafers. For example, a bonded wafer can include a top wafer (e.g., a device wafer) bonded to a carrier wafer. These bonded wafers can be used for both memory and logic applications. Three-dimensional integrated circuits (3D IC) can be produced using bonded wafers. [0006] Bonded wafers can have complex edge profiles. The various layers of a bonded wafer can have different heights and diameters. These dimensions can be affected by the size of the various wafers prior to stacking or by processing steps. [0007] Bonded wafers with fabrication errors can cause problems during manufacturing. For example, centricity of the bonded wafer affects the CMP process or increases handling risks. During CMP, centricity affects placement of the polishing pad with respect to the center of the bonded wafer and subsequent planarization. During wafer handling, the balance of a bonded wafer or clearance within manufacturing equipment can be affected by centricity of the bonded wafer. [0008] Concentricity measurement can ensure accurate alignment for optimal performance in hybrid bonding. As the interconnect density increases in microelectronic packages, the tolerances on concentricity may need resolution in the range of microns. Improper centricity can even ruin a bonded wafer or damage manufacturing equipment. If the bonded wafer is undercut, improperly bonded together, or contains too much glue, then the bonded wafer can break within the CMP tool, contaminating or damaging the CMP tool. Such contamination or damage leads to unwanted downtime or can even stop production within a semiconductor fab. [0009] Furthermore, a CMP process on a bonded wafer with improper centricity can result in undesired edge profiles on the bonded wafer. For example, too much or not enough material may be removed during a CMP process or the CMP process may result in undercuts, overhangs, or whiskers. These undesired edge profiles can affect device yield or can impact later manufacturing steps. [0010] It is difficult to measure offset in a bonded wafer. A wafer surface inspection tool or a wafer edge inspection tool module typically reports images of wafer periphery. This can use extrapolation and manual calculation based on a scale bar and field of view of the image, which may not be accurate or precise. There may be ten or more points to measure on each wafer, which can reduce throughput of the measurement process. Therefore, improved techniques for bonded wafer metrology and associated systems are needed. BRIEF SUMMARY OF THE DISCLOSURE [0011] A metrology system is provided in a first embodiment. The metrology system includes a stage configured support a bonded wafer. The bonded wafer has a top wafer disposed on a carrier wafer. An imaging system is configured to generate wafer edge profile images of a circumferential edge of the bonded wafer. The imaging system includes a light source configured to generate collimated light and a detector configured to generate the wafer edge profile images. A processor is in electronic communication with the imaging system. The processor is programmed to: receive the wafer edge profile images; convert the wafer edge profile images from