EP-4735910-A1 - ULTRASOUND IMAGING PROBE

Abstract

The invention relates to an ultrasonic imaging probe (100), comprising first (110), second (120) and third (130) circuits, wherein: - the first circuit (110) is an ultrasonic transduction circuit comprising an array of elementary ultrasonic transduction chips (111) each comprising an array of elementary ultrasonic transducers (113); - the second circuit (120) is a transceiver circuit comprising, for each elementary ultrasonic transduction chip (111), an elementary transceiver chip (121); and - the third circuit (130) is a digital pre-processing circuit comprising, for each elementary transceiver chip (121), an elementary digital pre-processing chip (131).

Inventors

• Douady, César

Assignees

• Doliam

Dates

Publication Date

20260506

Application Date

20240617

Claims (1)

1. CLAIMS 1. An ultrasound imaging probe (100) comprising first (110), second (120) and third (130) circuits, in which: - the first circuit (110) is an ultrasonic transduction circuit comprising a matrix of elementary chips (111) of ultrasonic transduction each comprising a matrix of elementary ultrasonic transducers (113); - the second circuit (120) is a transmission-reception circuit comprising, for each elementary ultrasonic transduction chip (111), a corresponding specific elementary transmission-reception chip (121) comprising, for each elementary ultrasonic transducer (113) of the elementary ultrasonic transduction chip (111), an elementary transmission-reception cell (123) electrically connected to an electrode (el) of the transducer (113); - in each elementary transceiver chip (121), the elementary transceiver cells (123) of the chip are distributed into several elementary transceiver groups each comprising N elementary transceiver cells (123), with N being an integer greater than or equal to 1; the probe comprises, for each elementary transceiver chip (121), for each elementary transceiver group of the chip, an analog preprocessing circuit (125) comprising N input terminals connected respectively to an output terminal (n3) of each elementary transceiver cell (123) of the elementary transceiver group, and M output terminals, with M less than or equal to NN; the probe comprises, for each elementary transceiver group of each elementary chip transceiver (121), M analog-to-digital converters (127) each having an input terminal and an output terminal (e2), the input terminals of the M analog-to-digital converters (127) being connected respectively to the M output terminals of the analog preprocessing circuit (125) of the elementary transceiver group; the third circuit (130) is a digital preprocessing circuit comprising, for each elementary transceiver chip (121), a corresponding specific elementary digital preprocessing chip (131) comprising, for each elementary transceiver group of the elementary transceiver chip (121), M elementary digital preprocessing cells (133) connected respectively to the output terminals of the M analog-to-digital converters (127) associated with the elementary transceiver group; - each elementary digital preprocessing chip (131) comprises one or more binary connection elements (e3) each intended to provide a serialized digital signal, connected to all of the elementary digital preprocessing cells of the chip via one or more serialization circuits (301), in which each elementary digital preprocessing cell (133) comprises an elementary memory circuit (311) and a calculation unit (313), and in which each elementary digital preprocessing chip (131) comprises a global control circuit (303) connected to respective control nodes of the MxN elementary digital preprocessing cells (133) of the chip (131) and adapted to control the execution of a sequence of operations by the elementary digital preprocessing cells (133) of the chip (131). 2. Probe (100) according to claim 1, in which, in each elementary digital preprocessing cell (133), the elementary memory circuit (311) is adapted to memorize the complete signal provided by the corresponding analog-digital converter (127) during a reception time window following an ultrasonic shot. 3. Probe (100) according to claim 1 or 2, in which each analog pre-processing circuit (125) is a combiner selector circuit adapted to provide, on each of its M output terminals, an analog summation, or superposition, of all or part of the signals applied to its N input terminals. 4. Probe (100) according to any one of claims 1 to 5. 3, in which each transmission-reception cell (123) comprises a transmission circuit (210) adapted to generate an electrical excitation signal applied to the electrode (el) of the associated elementary transducer (113). 5. Probe (100) according to any one of claims 1 to 5. 4, in which each transceiver cell (123) comprises a reception circuit (220) comprising an amplifier (221) having an input node connected to the electrode (el) of the elementary transducer (113) and an output node connected to the output terminal (n3) of the transceiver cell (123). 6. Probe (100) according to claim 5, in which, in each transmission-reception cell (123), the reception circuit (220) further comprises a delay circuit (225) configured to apply a delay of an adjustable duration to the output electrical signal of the transducer (113). 7. Probe (100) according to claim 6, in which each elementary digital preprocessing cell (133) comprises data input-output ports (315) for exchanging data between the elementary memory circuit (311) of the cell and the elementary memory circuits (311) of neighboring elementary cells (133). 8. A probe (100) according to any one of claims 1 to 7, wherein the first (110), second (120) and third (130) circuits are stacked vertically, the second circuit (120) being disposed between the first (110) and third (130) circuits. 9. A probe according to any one of claims 1 to 7, wherein two (110, 120) of the first (110), second (120) and third (130) circuits are stacked vertically, the remaining circuit (130) of the first (110), second (120) and third (130) circuits being offset laterally. 10. Probe (100) according to any one of claims 1 to 9, in which M is strictly less than N. 11. An ultrasound imaging system comprising an ultrasound imaging probe (100) according to any one of claims 1 to 10, an external processing device (160), and a digital data transmission channel (150) connecting the probe to the external processing device (160). 12. System according to claim 11, in which the digital data transmission channel (150) comprises one or more wired electrical or optical data transmission elements (151) per elementary digital preprocessing chip (131), electrically connected respectively to said one or more binary connection elements (e3) of the elementary chip. 13. The system of claim 11 or 12, wherein the external processing device (160) is configured to apply delays and combine signals from analog-to-digital converters (127).

Description

DESCRIPTION TITLE: Ultrasound imaging probe This application is based on, and claims priority from, French patent application No. 23/06703 filed on June 27, 2023 and entitled "Ultrasound imaging probe" which is considered to be an integral part of this description within the limits provided by law. Technical field [0001] The present description relates to the field of ultrasound imaging, and more particularly aims at an ultrasound imaging probe intended to be connected to an external control and processing system via a cable, the probe integrating a plurality of ultrasound transducers and electronic circuits for controlling these transducers. Previous technique [0002] Various architectures of ultrasound imaging probes have already been proposed. [0003] It would be desirable to improve at least in part certain aspects of known ultrasound imaging probes. [0004] We are more particularly interested here in the production of ultrasound imaging probes adapted to implement, as close as possible to the ultrasound sensor, digital and/or analog processing such as, for example, micro-beamforming processing, for example in the context of ultra-rapid acquisition scenarios. Summary of the invention [0005] One embodiment provides an ultrasound imaging wave having first, second, and third circuits, wherein: the first circuit is an ultrasonic transduction circuit comprising a matrix of elementary ultrasonic transduction chips each comprising a matrix of elementary ultrasonic transducers; - the second circuit is a transmit-receive circuit comprising, for each elementary ultrasonic transduction chip, a corresponding specific elementary transmit-receive chip comprising, for each elementary ultrasonic transducer of the elementary ultrasonic transduction chip, an elementary transmit-receive cell electrically connected to an electrode of the transducer; in each elementary transmit-receive chip, the elementary transmit-receive cells of the chip are distributed into several elementary transmit-receive groups each comprising N elementary transmit-receive cells, with N being an integer greater than or equal to 1; - the probe comprises, for each elementary emission-reception chip, for each elementary emission-reception group of the chip, an analog preprocessing circuit comprising N input terminals connected respectively to an output terminal of each elementary emission-reception cell of the elementary emission-reception group, and M output terminals, with M less than or equal to NN; the probe comprises, for each elementary emission-reception group of each elementary emission-reception chip, M analog-digital converters each having an input terminal and an output terminal, the input terminals of the M analog-digital converters being connected respectively to the M output terminals of the analog preprocessing circuit of the elementary emission-reception group; the third circuit is a preprocessing circuit digital comprising, for each elementary transmission-reception chip, a corresponding specific elementary digital preprocessing chip comprising, for each elementary transmission-reception group of the elementary transmission-reception chip, M elementary digital preprocessing cells connected respectively to the output terminals of the M analog-digital converters associated with the elementary transmission-reception group; - each elementary digital preprocessing chip comprises one or more binary connection elements each intended to provide a serialized digital signal, connected to all of the elementary digital preprocessing cells of the chip via one or more serialization circuits, in which each elementary digital preprocessing cell comprises an elementary memory circuit and a calculation unit, and in which each elementary digital preprocessing chip comprises a global control circuit connected to respective control nodes of the MxN elementary digital preprocessing cells of the chip and adapted to control the execution of a sequence of operations by the elementary digital preprocessing cells of the chip. [0006] According to one embodiment, in each elementary digital preprocessing cell the elementary memory circuit is adapted to memorize the complete signal provided by the corresponding analog-digital converter during a reception time window following an ultrasonic shot. [ 0007 ] According to one embodiment, each analog preprocessing circuit is a combiner selector circuit adapted to provide, on each of its M output terminals, a analog summation, or superposition, of all or part of the signals applied to its N input terminals. [0008] According to one embodiment, each transmission-reception cell comprises a transmission circuit adapted to generate an electrical excitation signal applied to the electrode of the associated elementary transducer. [0009] According to one embodiment, each transmission-reception cell comprises a reception circuit comprising an amplifier having an input node connected to the electrode of the elementary transducer an