EP-4735912-A1 - METHODS AND APPARATUS TO FORM AN IMAGE WITH DYNAMIC DELAY AND GAIN BEAMFORMING

Abstract

An example apparatus includes: analog-to-digital converter (ADC) circuitry (1105. 1110) having an output terminal; beamforming circuitry (1115) including: delay circuitry having a first input terminal, a second input terminal, and an output terminal, the first input terminal of the delay circuitry coupled to the output terminal of the ADC circuitry; amplifier circuitry (1165, 1180) having an input terminal and an output terminal, the input terminal of the amplifier circuitry coupled to the output terminal of the delay circuitry; and summation circuitry (1150) having an input terminal coupled to the output terminal of the amplifier circuitry: beamforming control circuitry (1120, 1204) coupled to the second input terminal of the delay circuitry, the beamforming control circuitry configured to calculate a delay value based on a piecewise delay profile.

Inventors

• NIMRAN, VAJEED
• AITHAL, SACHIN
• WALA, SHABBIR AMJHERA
• REJI, Rahul

Assignees

• Texas Instruments Incorporated

Dates

Publication Date

20260506

Application Date

20240627

Claims (20)

1. 1 . An apparatus comprising: analog-to-digital converter (ADC) circuitry having an output terminal; beamforming circuitry including: delay circuitry having a first input terminal, a second input terminal, and an output terminal, the first input terminal of the delay circuitry coupled to the output terminal of the ADC circuitry; amplifier circuitry having an input terminal and an output terminal, the input terminal of the amplifier circuitry coupled to the output terminal of the delay circuitry; and summation circuitry having an input terminal coupled to the output terminal of the amplifier circuitry; and beamforming control circuitry coupled to the second input terminal of the delay circuitry 7 , the beamforming control circuitry configured to calculate a delay value based on a piecewise delay profile and provide the delay value at the second input terminal of the delay circuitry.
2. 2. The apparatus of claim 1, wherein the delay circuitry is coarse delay circuitry, the beamforming circuitry 7 further including fine delay circuitry 7 having a first input terminal, a second input terminal, and an output terminal, the first input terminal of the fine delay circuitry is coupled to the output terminal of the coarse delay circuitry, the second input terminal of the fine delay circuitry is coupled to the beamforming control circuitry, and the output terminal of the fine delay circuitry 7 is coupled to the input terminal of the amplifier circuitry.
3. 3. The apparatus of claim 1, wherein the beamforming circuitry includes a plurality 7 of delay profiles having a plurality of segments and an initial delay value, and a segment of the plurality of segments has a segment duration and a slope value.
4. 4. The apparatus of claim 3, wherein the beamforming control circuitry includes accumulator circuitry 7 configured to determine the delay value of a focus point by accumulating the slope value starting from the initial delay value based on a depth of the focus point in an image.
5. 5. The apparatus of claim 1, wherein the input terminal of the amplifier circuitry' is a first input terminal, the amplifier circuitry' further having a second input terminal, the beamforming control circuitry is coupled to the second input terminal of the amplifier circuitry, and the beamforming control circuitry further configured to calculate a gain value based on a piecewise expansion profile and a reference gain profile.
6. 6. The apparatus of claim 5, wherein the piecewise expansion profile includes a plurality of segments and an initial expansion factor, a segment of the plurality of segments has a segment duration and a slope value, and the beamforming control circuitry includes: accumulator circuitry configured to determine an expansion factor for a channel and a focus point by accumulating the slope value starting from the initial expansion factor based on a location of the focus point in an image; and indexer circuitry configured to determine a gain value for the channel and the focus point by at least one of expanding or compressing gain values of the reference gain profile.
7. 7. The apparatus of claim 1, wherein the ADC circuitry further having an input terminal, the summation circuitry further having an output terminal, and the apparatus is further comprising: transmitter circuitry having an input terminal and an output terminal; a transducer having a terminal coupled to the input terminal of the ADC circuitry and the output terminal of the transmitter circuitry; and programmable circuitry having an input terminal and an output terminal, the input terminal of the programmable circuitry is coupled to the output terminal of the summation circuitry, the output terminal of the programmable circuitry is coupled to the input terminal of the transmitter circuitry 7 .
8. 8. An apparatus comprising: analog-to-digital converter (ADC) circuitry having an output terminal; beamforming circuitry including: delay circuitry having an input terminal and an output terminal, the input terminal of the delay circuitry coupled to the output terminal of the ADC circuitry; amplifier circuitry having a first input terminal, a second input terminal, and an output terminal, the first input terminal of the amplifier circuitry coupled to the output terminal of the delay circuitry; and summation circuitry ■ having an input terminal and an output terminal, the input terminal of the summation circuitry 7 coupled to the output terminal of the amplifier circuitry; and beamforming control circuitry coupled to the second input terminal of the amplifier circuitry, the beamforming control circuitry configured to calculate a gain value based on a reference gain profile and a pieceyvise expansion profile.
9. 9. The apparatus of claim 8, wherein the delay circuitry is coarse delay circuitry 7 , the beamforming circuitry further including fine delay circuitry having a first input terminal, a second input terminal, and an output terminal, the first input terminal of the fine delay circuitry is coupled to the output terminal of the coarse delay circuitry, the second input terminal of the fine delay circuitry is coupled to the beamforming control circuitry, and the output terminal of the fine delay circuitry is coupled to the input terminal of the amplifier circuitry.
10. 10. The apparatus of claim 8, wherein the piecewise expansion profile includes a plurality of segments and an initial expansion factor, a segment of the plurality of segments has a segment duration and a slope value.
11. 11. The apparatus of claim 10. wherein the beamforming control circuitry includes: accumulator circuitry configured to determine an expansion factor for a channel and a focus point by accumulating the slope value starting from the initial expansion factor based on a location of the focus point in an image; and indexer circuitry configured to determine a gain value for the channel and the focus point by at least one of expanding or compressing gain values of the reference gain profile.
12. 12. The apparatus of claim 8, wherein the input terminal of the delay circuitry is a first input terminal, the delay circuitry further having a second input terminal, the beamforming control circuitry is coupled to the second input terminal of the delay circuitry, and the beamforming control circuitry further configured to calculate a delay value based on a piecewise delay profile.
13. 13. The apparatus of claim 12, wherein the piecewise delay profile has a plurality' of segments and an initial delay value, a segment of the plurality of segments has a segment duration and a slope value, and the beamforming control circuitry includes accumulator circuitry configured to determine the delay value of a focus point by accumulating the slope value starting from the initial delay value based on a depth of the focus point in an image.
14. 14. The apparatus of claim 8, wherein the ADC circuitry' further having an input terminal, the summation circuitry’ further having an output terminal, and the apparatus is further comprising: transmitter circuitry having an input terminal and an output terminal; a transducer having a terminal coupled to the input terminal of the ADC circuitry' and the output terminal of the transmitter circuitry; and programmable circuitry having an input terminal and an output terminal, the input terminal of the programmable circuitry is coupled to the output terminal of the summation circuitry’, the output terminal of the programmable circuitry' is coupled to the input terminal of the transmitter circuitry'.
15. 15. An apparatus comprising: a transducer having a terminal; memory' circuitry including a portion of memory' having piecewise delay profdes; analog-to-digital converter (ADC) circuitry having an input terminal and an output terminal, the input terminal of the ADC circuitry coupled to the terminal of the transducer; and beamforming circuitry including: delay circuitry' having a first input terminal, a second input terminal, and an output terminal, the first input terminal of the delay circuitry coupled to the output terminal of the ADC circuitry, the second input terminal of the delay circuitry coupled to the portion of memory 7 ; amplifier circuitry 7 having an input terminal and an output terminal, the input terminal of the amplifier circuitry' coupled to the output terminal of the delay circuitry'; and summation circuitry having an input terminal coupled to the output terminal of the amplifier circuitry.
16. 16. The apparatus of claim 15, wherein the piecewise delay profiles include a plurality' of delay profiles having a plurality of segments and an initial delay value, and a segment of the plurality of segments has a segment duration and a slope value.
17. 17. The apparatus of claim 16, further comprising accumulator circuitry' configured to determine a delay value of a focus point by accumulating the slope value starting from the initial delay value based on a depth of the focus point in an image.
18. 18. The apparatus of claim 15. wherein the input terminal of the portion of memory is a first portion of memory, the memory 7 circuitry further including: a second portion of memory 7 having a reference gain profile; and a third portion of memory having a piecewise expansion profile, the piecewise expansion profile includes a plurality' of segments and an initial expansion factor, a segment of the plurality of segments has a segment duration and a slope value.
19. 19. The apparatus of claim 18, further comprising: accumulator circuitry configured to determine an expansion factor for a channel and a focus point by accumulating the slope value starting from the initial expansion factor based on a location of the focus point in an image; and indexer circuitry configured to determine a gain value for the channel and the focus point by at least one of expanding or compressing gain values of the reference gain profile.
20. 20. The apparatus of claim 15, wherein the summation circuitry further having an output terminal, and the apparatus is further comprising: transmitter circuitry having an input terminal and an output terminal, the output terminal of the transmitter circuitry is coupled to the terminal of the transducer and the input terminal of the ADC circuitry; and programmable circuitry having an input terminal and an output terminal, the input terminal of the programmable circuitry is coupled to the output terminal of the summation circuitry 7 , the output terminal of the programmable circuitry is coupled to the input terminal of the transmitter circuitry 7 .

Description

METHODS AND APPARATUS TO FORM AN IMAGE WITH DYNAMIC DELAY AND GAIN BEAMFORMING [0001] This description relates generally to beamforming and, more particularly, to methods and apparatus to form an image with dynamic delay and gain beamforming. BACKGROUND [0002] In beamforming circuitry, increasingly complex beamforming operations allow systems to support higher quality imaging and higher operating speeds. Such operations allow the beamforming circuitry to accurately support a wide range of imaging operations. SUMMARY [0003] For methods and apparatus to form an image with dynamic delay and gain beamforming, an example apparatus includes analog-to-digital converter (ADC) circuitry having an output terminal; beamforming circuitry including: delay circuitry having a first input terminal, a second input terminal, and an output terminal, the first input terminal of the delay circuitry coupled to the output terminal of the ADC circuitry; amplifier circuitry having an input terminal and an output terminal, the input terminal of the amplifier circuitry coupled to the output terminal of the delay circuitry; and summation circuitry having an input terminal coupled to the output terminal of the amplifier circuitry: and beamforming control circuitry coupled to the second input terminal of the delay circuitry, the beamforming control circuitry configured to calculate a delay value based on a piecewise delay profile. Other examples are described. [0004] For methods and apparatus to form an image with dynamic delay and gain beamforming, an example apparatus includes analog-to-digital converter (ADC) circuitry having an output terminal; beamforming circuitry’ including: delay circuitry having an input terminal and an output terminal, the input terminal of the delay circuitry coupled to the output terminal of the ADC circuitry; amplifier circuitry having a first input terminal, a second input terminal, and an output terminal, the first input terminal of the amplifier circuitry coupled to the output terminal of the delay circuitry; and summation circuitry’ having an input terminal and an output terminal, the input terminal of the summation circuitry coupled to the output terminal of the amplifier circuitry; and beamforming control circuitry coupled to the second input terminal of the amplifier circuitry, the beamforming control circuitry’ configured to calculate a gain value based on a reference gain profile and a piecewise expansion profile. Other examples are described. [0005] For methods and apparatus to form an image with dynamic delay and gain beamforming, an example apparatus includes a transducer having a terminal; memory circuitry including a portion of memory' having piecewise delay profiles; analog-to-digital converter (ADC) circuitry’ having an input terminal and an output terminal, the input terminal of the ADC circuitry coupled to the terminal of the transducer; and beamforming circuitry including: delay circuitry having a first input terminal, a second input terminal, and an output terminal, the first input terminal of the delay circuitry’ coupled to the output terminal of the ADC circuitry', the second input terminal of the delay circuitry coupled to the portion of memory; amplifier circuitry having an input terminal and an output terminal, the input terminal of the amplifier circuitry coupled to the output terminal of the delay circuitry; and summation circuitry having an input terminal coupled to the output terminal of the amplifier circuitry’. Other examples are described. BRIEF DESCRIPTION OF THE DRAWINGS [0006] FIG. 1 is a block diagram of an example ultrasound system including example analog front-end circuitry having example beamforming circuitry, which constructs an image using beamforming. [0007] FIG. 2 is an example of the image of FIG. 1. [0008] FIG. 3 A is an example of continuous delay profiles of the image of FIG. 2. [0009] FIG. 3B is an example of piecewise delay profiles of the continuous delay profiles of FIG. 3A. [0010] FIG. 4A is an example of gain profiles of the image of FIG. 2. [0011] FIG. 4B is an example reference apodization profile of the image of FIG. 2. [0012] FIG. 5A is an example continuous expansion profile of the reference gain profile of FIG. 4B. [0013] FIG. 5B is an example piecewise expansion profile of the continuous expansion profile of FIG. 5 A. [0014] FIG. 6 is a block diagram of example piecewise beamforming compiler circuitry which generates the piecewise delay profiles of FIG. 3B and the piecewise expansion profile of FIG. 5B for beamforming. [0015] FIG. 7 is a flowchart representative of example machine-readable instructions or example operations that may be at least one of executed, instantiated, or performed using an example programmable circuitry implementation of the piecewise beamforming compiler circuitry of FIG. 6. [0016] FIG. 8 is a flowchart representative of example machine-readable instructions or example operations that may be at least one of executed, i