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EP-4735974-A1 - CONFIGURABLE MESH NETWORK NODE AGGREGATION FOR MITIGATING VOLTAGE DROOP IN AN INTEGRATED CIRCUIT (IC) CHIP AND RELATED METHODS

EP4735974A1EP 4735974 A1EP4735974 A1EP 4735974A1EP-4735974-A1

Abstract

Aggregation circuits provided in each of the nodes of an IC chip are employed to, based on indications of power consumption in an aggregation zone of the IC chip, reduce power consumption in the nodes in the aggregation zone to mitigate voltage droop. Each aggregation zone includes a first node that receives indications of power consumption associated with the first node and indications of power consumption associated with other nodes in the aggregation zone. The first node generates a control signal based on the received indications, and each of the plurality of nodes in the aggregation zone reduces power consumption based on the control signal. In some examples, the aggregation circuit in any node may be configured to operate in a first mode as the first node or in a second mode as one of the second nodes, providing flexibility in the configuration of aggregation zones.

Inventors

  • THOMAS, Ann Hampton
  • HOFMANN, RICHARD GERARD
  • BASNIGHT, THOMAS
  • EL-TANANI, Mohammed A.

Assignees

  • Microsoft Technology Licensing, LLC

Dates

Publication Date
20260506
Application Date
20240621

Claims (20)

  1. 1. An integrated circuit (IC) chip (100) comprising: a plurality' of nodes (502(l)-502(N)) in a mesh network; a first aggregation zone (504(1)) comprising a first node (510) and at least a second node (512(l)-512(F)) of the plurality' of nodes (502(l)-502(N)). wherein: each node of the plurality of nodes (502(l)-502(N)) comprises an aggregation circuit (400) configured to receive a first indication of power consumption (414P) associated with the node; the aggregation circuit (400) in the first node (510) is configured to, in response to operating in a first mode: receive at least a second indication of power consumption (414P) associated with each of the at least a second node (512(1)-512(F)); and provide a first control signal (416C) based on the first indication (414P) and the at least a second indication (414P) to each node of the at least a second node (512(1)-512(F)); and the aggregation circuit (400) in each of the first node (510) and the at least a second node (512(1)-512(F)) is configured to reduce power consumption in the node in response to the first control signal (416C).
  2. 2. The IC chip of claim 1, the aggregation circuit in each node of the plurality of nodes, comprises a configuration register configured to selectively control the aggregation circuit to operate in one of the first mode and a second mode.
  3. 3. The IC chip of claim 1 or claim 2, yvherein the aggregation circuit in each of the at least a second node is configured to operate in the second mode.
  4. 4. The IC chip of any of claim 1 to claim 3, further comprising at least a second aggregation zone comprising a third node and at least a fourth node, wherein: the aggregation circuit in the third node is configured to operate in the first mode; and the aggregation circuit in each of the third node and the at least a fourth node is configured to reduce power consumption in the node in response to a second control signal provided by the third node.
  5. 5. The IC chip of any of claim 1 to claim 4, yvherein: the mesh network further comprises segments, each coupled betyveen two nodes of the plurality of nodes adjacent to each other; and each node of the plurality of nodes is coupled to at least two segments of the mesh network.
  6. 6. The IC chip of any of claim 1 to claim 5, wherein the first node in the first aggregation zone is adjacent to each of the at least a second node.
  7. 7. The IC chip of any of claim 1 to claim 6, wherein the at least a second node comprises up to four nodes of the plurality of nodes adjacent to the first node.
  8. 8. The IC chip of claim 7, wherein the aggregation circuit in the first node is further configured to identify each node of the at least a second node among the plurality of nodes adj acent to the first node.
  9. 9. The IC chip of any of claims 1 , 2, and 4 to 8, wherein: the first aggregation zone further comprises at least a fifth node; each node of the at least a fifth node is adjacent to one of the at least a second node; the aggregation circuit in each of the at least a second node adjacent to at least one of the at least a fifth node is configured to: receive at least a third indication of power consumption associated with each of the at least one of the at least a fifth node; provide the at least a third indication to the first node; and provide the first control signal to each of the at least one of the at least a fifth node; and the first node is further configured to provide the first control signal based on the at least a third indication.
  10. 10. The IC chip of claim 9, wherein: the aggregation circuit in each node of the plurality of nodes is further configured to selectively control the aggregation circuit to operate in a third mode; each of the at least a second node comprises the aggregation circuit configured to operate in the third mode; and the aggregation circuit in each of the at least a fifth node is configured to operate in the second mode.
  11. 11. The IC chip of any of claim 1 to claim 10, wherein: the first aggregation zone comprises the plurality of nodes on the IC chip; the mesh network extends over a first area of the IC chip; and the first node is disposed in a center portion of the first area.
  12. 12. The IC chip of any of claim 1 to claim 11. further comprising a voltage comparator configured to compare a power supply voltage to a threshold, wherein in each node of the plurality of nodes, the first indication of power consumption associated with the node comprises an output from the voltage comparator.
  13. 13. The IC chip of any of claim 1 to claim 12, wherein: at least one node of the plurality of nodes is coupled to a corresponding processing circuit; and in the at least one node coupled to a corresponding processing circuit, the first indication of power consumption associated with the node comprises an indication from the corresponding processing circuit of an event related to a data transmission.
  14. 14. The IC chip of any of claim 1 to claim 13, wherein: each node of the plurality of nodes further comprises a plurality of router circuits configured to transmit data on a segment of the mesh netw ork; and in each node of the plurality of nodes, reducing power consumption in the node comprises inhibiting data transmissions from at least a subset of the plurality of router circuits in the node.
  15. 15. A method in an integrated circuit (IC) chip (100), the method comprising: in a first aggregation zone (504(1)) comprising a first node (510) and at least a second node (512(l)-512(F)) of a plurality of nodes (502(1 )-502(N)) in a mesh network (304), receiving, in an aggregation circuit (400) in each node of the plurality of nodes (502(l)-502(N)), a first indication of power consumption (414P) associated with the node; in response to the aggregation circuit (400) in the first node (510) configured to operate in a first mode: receiving, in the first node (510), at least a second indication of power consumption (414P) associated with each of the at least a second node (512(1)-512(F)); and providing a first control signal (416C) based on the first indication (414P) and the at least a second indication (414P) to each node of the at least a second node (512(1)-512(F)); and in the aggregation circuit (400) in each of the first node (510) and the at least a second node (512(1)-512(F)), reducing power consumption in the node in response to the first control signal (416C).
  16. 16. The method of claim 15, further comprising, in each node of the plurality of nodes, configuring a configuration register to selectively control the aggregation circuit to operate in one of the first mode and a second mode.
  17. 17. The method of claim 15 or claim 16, further comprising configuring the aggregation circuit in each of the at least a second node to operate in the second mode.
  18. 18. The method of any of claim 15 to claim 17, further comprising, in a second aggregation zone comprising a third node and at least a fourth node: configuring the aggregation circuit in the third node to operate in the first mode; and in the aggregation circuit in each node of the third node and the at least a fourth node, reducing power consumption in the node in response to a second control signal provided by the third node.
  19. 19. The method of any of claim 15 to claim 18, further comprising: configuring the aggregation circuit in each node of the at least a second node to: receive at least a third indication of power consumption associated with one of at least a fifth node coupled to the node; provide the at least a third indication to the first node; and provide the first control signal to each of the at least one of the at least a fifth node; and providing, by the first node, the first control signal based on the at least a third indication.
  20. 20. The method of any of claim 15 to claim 19, wherein, in each node of the plurality of nodes, reducing power consumption in the node comprises inhibiting data transmissions from at least a subset of a plurality 7 of router circuits configured to transmit data from the node.

Description

CONFIGURABLE MESH NETWORK NODE AGGREGATION FOR MITIGATING VOLTAGE DROOP IN AN INTEGRATED CIRCUIT (IC) CHIP AND RELATED METHODS Field of the Disclosure [0001] The technology of the disclosure relates generally to reducing voltage droop in an integrated circuit and, more particularly, to minimizing current spikes by controlling circuit switching. Background [0002] To reduce the package sizes of technologies employed for high-performance processing capabilities, the number of processing circuits provided in an integrated circuit (IC) chip has continued to increase. Communication of data among the many processing circuits can create congestion in the IC chip. One approach to handling data processed by the many processing circuits is to employ a mesh network in which each of the processing circuits is coupled to a node of the network and data is passed from node to node over segments of the network. In the nodes, the number of circuits switching due to data transmissions in a given system clock cycle varies from node to node depending on the respective processing circuits. Thus, the power needs among the nodes can shift frequently and the power levels in regions of the IC chip can rise suddenly. In such situations, the demand for current on the power rail providing a power supply voltage to these regions increases suddenly. Capacitance of the power distribution network within the IC chip may discharge in response to a sudden current increase, causing a voltage level on the power supply rail to droop temporarily. To avoid having the power supply voltage on the power rail drop below a minimum voltage, below which the processing circuits may not continue to operate normally, the nominal voltage level maintained on the power rail may be constantly maintained at a higher level to provide a voltage margin. However, maintaining a higher nominal voltage level on the power rail increases the power consumption of the IC chip, which may cause heat-related problems and will reduce battery life in mobile devices. Circuits and methods for avoiding voltage droop in the nodes in a mesh network without simply increasing power supply voltage to the entire IC chip would save power and avoid excessive heat generation. Summary [0003] Aspects disclosed in the detailed description include configurable mesh network node aggregation for mitigating voltage droop in an integrated circuit (IC) chip. Related methods of configurably aggregating mesh network nodes to mitigate voltage droop are also disclosed. A sudden increase in the demand for current in a node in a mesh network on an IC chip, known as a di/dt event, can cause a droop in the power supply voltage in a power supply rail coupled to the node. This problem may occur in individual nodes or in regions of the IC chip due to data transmissions among multiple adjacent nodes on the mesh network. The IC chip may have multiple such regions, which can be identified through testing. Exemplary aggregation circuits provided in each of the nodes of the IC chip can be employed to, based on indications of power consumption in an aggregation zone of the IC chip, reduce power consumption in the nodes in the aggregation zone to mitigate voltage droop. In particular, each aggregation zone includes a first node (also referred to herein as a “leader’’ node) that receives indications of power consumption associated with the first node and indications of power consumption associated with each of the other nodes in the aggregation zone. The first node generates a control signal based on the received indications, and each of the plurality of nodes in the aggregation zone reduces power consumption based on the control signal. In some examples, the aggregation circuit in any node may be configured to operate in a first, leader mode or in a second, follower mode, providing flexi bi li ty in the configuration of aggregation zones. In some examples, the aggregation circuits in some nodes in an aggregation zone are configured in a third, middle mode that receives the indications of power consumption from nodes in the second, follower mode and provides the indications to the first node. In addition, in such examples, the nodes in the third, middle mode can receive the control signal from the first node and provide the first control signal to the nodes in the second, follower mode. [0004] In this regard, an IC chip is disclosed. The IC chip includes a plurality of nodes in a mesh network. The IC chip further includes a first aggregation zone comprising a first node and at least a second node of the plurality of nodes wherein each node of the plurality' of nodes comprises an aggregation circuit configured to receive a first indication of power consumption associated with the node, the aggregation circuit in the first node is configured to, in response to operating in a first mode: receive at least a second indication of power consumption associated with each of the at least a second node and provide a first con