EP-4735975-A1 - HETEROGENEOUS CHIPLET POWER MANAGEMENT

Abstract

The disclosed device includes heterogeneous chiplets that can communicate when each of the heterogenous chiplets has locally reached an idle state. Once receiving confirmations of the idle state from each of the heterogenous chiplets, the chiplets can complete the entry of the low power state. Various other methods, systems, and computer-readable media are also disclosed.

Inventors

• TSIEN, BENJAMIN

Assignees

• Advanced Micro Devices, Inc.

Dates

Publication Date

20260506

Application Date

20240627

Claims (20)

1. 1. A device comprising: a plurality of heterogeneous chiplets, wherein a first chiplet of the plurality of heterogeneous chiplets is configured to: report, to a second chiplet of the plurality of heterogeneous chiplets in response to receiving an indication of the device initiating entry of a low power state, locally reaching an idle state; and in response to receiving a confirmation of the idle state from the second chiplet, locally complete the entry of the low power state.
2. 2. The device of claim 1 , wherein the first chiplet corresponds to a stutter client chiplet having an activity buffer and locally reaching the idle state includes filling the activity buffer based on a buffer threshold.
3. 3. The device of claim 2, wherein the buffer threshold corresponds to a minimum idle period before the stutter client chiplet wakes up to refill the activity buffer.
4. 4. The device of claim 2, wherein the stutter client chiplet corresponds to a display engine and the activity buffer corresponds to a display buffer.
5. 5. The device of claim 2, wherein the stutter client chiplet corresponds to a multimedia engine and the activity buffer corresponds to a multimedia buffer.
6. 6. The device of claim 2, wherein the stutter client chiplet is configured to receive an indication of the device transitioning to a partial power state in which a subset of logic components of the stutter client chiplet is active to allow filling the activity buffer, and wherein other chiplets of the plurality of heterogenous chiplets remain idle.
7. 7. The device of claim 6, wherein the plurality of heterogeneous chiplets are configured to abort, in response to at least one of the plurality of heterogeneous chiplets broadcasting an active state, transitioning to the partial power state while the stutter client chiplet is filling the activity buffer.
8. 8. The device of claim 1, wherein locally reaching the idle state comprises at least one of saving a state, disabling write burst accumulation, or flushing remaining writes.
9. 9. The device of claim 1, wherein the plurality of heterogeneous chiplets are configured to abort the entry of the low power state in response to at least one of the plurality of heterogeneous chiplets broadcasting an active state.
10. 10. A system comprising: a plurality of heterogeneous chiplets including a stutter client having an activity buffer; and a control circuit configured to: in response to the system initiating entry of a low power state, confirm each of the plurality of heterogenous chiplets has locally reached an idle state; in response to receiving confirmations of the idle state from each of the plurality of heterogenous chiplets, instruct the stutter client to fill the activity buffer to a buffer threshold; and in response to the stutter client filling the activity buffer, complete entry of the low power state.
11. 11. The system of claim 10, wherein the buffer threshold corresponds to a minimum idle period before the stutter client wakes up to refill the activity buffer.
12. 12. The system of claim 11, wherein refilling the activity buffer further comprises accessing a memory of the system.
13. 13. The system of claim 10, wherein the stutter client corresponds to a display engine and the activity buffer corresponds to a display buffer.
14. 14. The system of claim 10, wherein the control circuit is configured to: receive an indication of a partial power state in which only components servicing the stutter client is active; and in response to the indication, instructing the stutter client and a corresponding link to power on, wherein other chiplets of the plurality of heterogenous chiplets remain idle.
15. 15. The system of claim 14, wherein the control circuit is configured to, in response to at least one of the plurality of heterogeneous chiplets broadcasting an active state, abort the partial power state.
16. 16. The system of claim 10, wherein the control circuit is configured to abort, in response to at least one of the plurality of heterogeneous chiplets broadcasting an active state, entry of the low power state.
17. 17. A method comprising: transitioning a plurality of heterogeneous chiplets to a new power state that corresponds to power gating idle chiplets of the plurality of heterogeneous chiplets; confirming, while a stutter client chiplet of the plurality of heterogeneous chiplets is kept at least partially powered on, the idle chiplets have completed operations for reaching an idle state; and in response to confirmations from the idle chiplets of the idle state, completing the transition to the new power state.
18. 18. The method of claim 17, wherein the stutter client chiplet has an activity buffer and the stutter client chiplet is kept at least partially powered on to fill the activity buffer to at least a buffer threshold.
19. 19. The method of claim 18, further comprising aborting the transition to the new power state while the stutter client chiplet fills the activity buffer.
20. 20. The method of claim 17, wherein the operations includes at least one of confirming corresponding local clients are idle, saving a state, flushing writes, disabling write burst accumulation, or confirming a corresponding fabric is idle.

Description

HETEROGENEOUS CHIPEET POWER MANAGEMENT BACKGROUND [0001] Power management for processor architectures, such as a system-on-chip (SOC), often involve placing the SOC in a low power state. To place the SOC in the low power state, the various components within the SOC would synchronize to reach an idle state (e.g., a state of low or no activity) to allow power gating. For a monolithic SOC or SOC with a homogeneous chiplet architecture, having the various chiplets reach the idle state can follow similar processes. However, for a heterogeneous chiplet architecture, which can include a mix of chiplets having real-time traffic with other types of chiplets, coordinating the chiplets can be difficult. BRIEF DESCRIPTION OF THE DRAWINGS [0002] The accompanying drawings illustrate a number of exemplary implementations and are a part of the specification. Together with the following description, these drawings demonstrate and explain various principles of the present disclosure. [0003] FIG. 1 is a block diagram of an exemplary system for heterogeneous chiplet power management. [0004] FIG. 2 is a block diagram of an exemplary architecture for heterogeneous chiplets. [0005] FIGS. 3A-C are block diagrams of exemplary workflows for heterogeneous chiplet power management. [0006] FIG. 4 is a flow diagram of another exemplary workflow for heterogeneous chiplet power management. [0007] FIG. 5 is a flow diagram of an exemplary method for heterogeneous chiplet power management. [0008] Throughout the drawings, identical reference characters and descriptions indicate similar, but not necessarily identical, elements. While the exemplary implementations described herein are susceptible to various modifications and alternative forms, specific implementations have been shown by way of example in the drawings and will be described in detail herein. However, the exemplary implementations described herein are not intended to be limited to the particular forms disclosed. Rather, the present disclosure covers all modifications, equivalents, and alternatives falling within the scope of the appended claims. DETAILED DESCRIPTION [0009] The present disclosure is generally directed to heterogeneous chiplet power management. As will be explained in greater detail below, implementations of the present disclosure instruct heterogeneous chiplets to reach an idle state individually and locally in response to initiating entry of a low power state. After confirming that each chiplet is idle, the entry to the low power state can be completed. Advantageously, this allows stutter clients (e.g., chiplets that can perform in bursts of activity/ data) to coordinate with other chiplets for low power states and/or partial low power states, enabling improved power management for heterogeneous chiplet architectures. [0010] In one implementation, a device for heterogeneous chiplet power management includes a plurality of heterogeneous chiplets. A first chiplet of the plurality of heterogeneous chiplets is configured to report, to a second chiplet of the plurality of heterogeneous chiplets in response to receiving an indication of the device initiating entry of a low power state, locally reaching an idle state, and in response to receiving a confirmation of the idle state from the second chiplet, locally complete the entry of the low power state. [0011] In some examples, the first chiplet corresponds to a stutter client chiplet having an activity buffer and locally reaching the idle state includes filling the activity buffer based on a buffer threshold. In some examples, the buffer threshold corresponds to a minimum idle period before the at least one chiplet wakes up to refill the activity buffer. In some examples, the stutter client chiplet corresponds to a display engine and the activity buffer corresponds to a display buffer. In some examples, the stutter client chiplet corresponds to a multimedia engine and the activity buffer corresponds to a multimedia buffer. [0012] In some examples, the stutter client chiplet is configured to receive an indication of the device transitioning to a partial power state in which a subset of logic components of the stutter client chiplet is active to allow filling the activity buffer, and wherein other chiplets of the plurality of heterogenous chiplets remain idle. In some examples, the plurality of heterogeneous chiplets are configured to abort, in response to at least one of the plurality of heterogeneous chiplets broadcasting an active state, transitioning to the partial power state while the stutter client chiplet is filling the activity buffer. [0013] In some examples, locally reaching the idle state comprises at least one of saving a state, disabling write burst accumulation, flushing remaining writes. In some examples, the plurality of heterogeneous chiplets are configured to abort the entry of the low power state in response to at least one of the plurality of heterogeneous chiplets broadcasting an active state. [0