EP-4735988-A1 - LOW POWER MEMORY STATE DURING NON-IDLE PROCESSOR STATE

Abstract

The disclosed device includes multiple processing component, and a cache. One of the processing components can be instructed to avoid allocating to the cache and another of the processing components can be allowed use the cache while reducing accessing a memory. The memory can then enter a low power state in response to an idle state of the memory from the processing components avoiding accessing the memory for a period of time. Various other methods, systems, and computer-readable media are also disclosed.

Inventors

• TSIEN, BENJAMIN
• PATEL, Chintan S.
• KRISHNAN, GUHAN

Assignees

• Advanced Micro Devices, Inc.

Dates

Publication Date

20260506

Application Date

20240627

Claims (20)

1. 1. A device comprising: a first processing component; a second processing component; a cache; and a control circuit configured to: instruct the first processing component to avoid allocating in the cache in response to cache misses; instruct the second processing component to allocate in the cache; and instruct a memory device to enter a low power state in response to an idle state of the memory device.
2. 2. The device of claim 1, wherein the control circuit is further configured to instruct the first processing component to force evictions from the cache in response to cache hits.
3. 3. The device of claim 1 , wherein the first processing component comprises an activity buffer and is configured to fill the activity buffer to a buffer threshold by accessing the memory device.
4. 4. The device of claim 3, wherein the idle state in the memory device corresponds to the first processing component pausing accesses to the memory device while the activity buffer is exhausted.
5. 5. The device of claim 3, wherein the first processing component corresponds to a display engine and the activity buffer corresponds to a display buffer.
6. 6. The device of claim 1 , wherein the first processing component avoiding allocating to the cache allows the second processing component to allocate a workload of the second processing component in the cache.
7. 7. The device of claim 6, wherein the idle state of the memory device corresponds to the second processing component avoiding accesses to the memory device by having the workload of the second processing component allocated in the cache.
8. 8. The device of claim 1, wherein the idle state of the memory device coincides with an active state of the second processing component.
9. 9. The device of claim 1, wherein the control circuit is further configured to instruct the memory device to enter the low power state in response to predicting that the idle state of the memory device has a sufficient idle duration.
10. 10. A system comprising: a memory; a processor comprising: a cache; a first processing component utilizing an activity buffer; and a second processing component; and a control circuit configured to: instruct the first processing component to use the activity buffer and avoid allocating in the cache in response to cache misses and force eviction from the cache in response to cache hits; instruct the second processing component to allocate in the cache; and instruct the memory to enter a low power state while the second processing component is active.
11. 11. The system of claim 10, wherein the control circuit is further configured to instruct the memory to enter the low power state in response to the memory entering an idle state.
12. 12. The system of claim 11, wherein the control circuit is further configured to instruct the memory to enter the low power state in response to predicting that the idle state of the memory has a sufficient idle duration.
13. 13. The system of claim 11, wherein the first processing component is configured to fill the activity buffer to a buffer threshold by accessing the memory, and an idle state of the memory corresponds to the first processing component pausing accesses to the memory while the activity buffer is exhausted.
14. 14. The system of claim 11 , wherein the first processing component avoiding allocating to the cache and forcing eviction from the cache allows the second processing component to allocate a workload of the second processing component in the cache.
15. 15. The system of claim 14, wherein the idle state of the memory corresponds to the second processing component avoiding accesses to the memory by having the workload of the second processing component allocated in the cache.
16. 16. The system of claim 10, wherein the first processing component corresponds to a display engine and the activity buffer corresponds to a display buffer.
17. 17. A method comprising: filling, by a first processing component, an activity buffer of the first processing component and reducing a workload footprint of the first processing component in a cache; avoiding accesses, by the first processing component, to a memory by exhausting the activity buffer; accessing the cache by a second processing component having its workload in the cache; and entering a low power state of the memory while the second processing component is active.
18. 18. The method of claim 17, further comprising filling the activity buffer to a buffer threshold by accessing the memory.
19. 19. The method of claim 17, wherein entering the low power state of the memory is in response to the memory being idle from the first processing component avoiding accesses to the memory and the second processing component avoiding accesses to the memory.
20. 20. The method of claim 17, wherein entering the low power state of the memory is in response to predicting the memory to be idle for a sufficient idle duration.

Description

LOW POWER MEMORY STATE DURING NON-IDLE PROCESSOR STATE BACKGROUND [0001] Under certain conditions, such as idle conditions, a processor can enter a low power state (e.g., by shutting off some or all of its components) to reduce power consumption. Similarly, a memory, such as a DRAM, can enter a low power state (e.g., a self-refresh in which data values are read and rewritten in order to refresh weakening charges). The memory low power state is often linked to processor idle states because the memory low power state often requires a period of time when the processor does not access the memory. However, certain architectures can reduce opportunities for the memory to enter the low power memory state. BRIEF DESCRIPTION OF THE DRAWINGS [0002] The accompanying drawings illustrate a number of exemplary implementations and are a part of the specification. Together with the following description, these drawings demonstrate and explain various principles of the present disclosure. [0003] FIG. 1 is a block diagram of an exemplary system for entering a low power memory state during a non-idle processor state. [0004] FIG. 2 is a block diagram of another exemplary system for entering a low power memory state during a non-idle processor state. [0005] FIG. 3 is a flow diagram of an exemplary method for entering a low power memory state during a non-idle processor state. [0006] FIG. 4 is a flow diagram of another exemplary method for entering a low power memory state during a non-idle processor state. [0007] Throughout the drawings, identical reference characters and descriptions indicate similar, but not necessarily identical, elements. While the exemplary implementations described herein are susceptible to various modifications and alternative forms, specific implementations have been shown by way of example in the drawings and will be described in detail herein. However, the exemplary implementations described herein are not intended to be limited to the particular forms disclosed. Rather, the present disclosure covers all modifications, equivalents, and alternatives falling within the scope of the appended claims. DETAILED DESCRIPTION [0008] The present disclosure is generally directed to entering a low power memory state during a non-idle processor state. As will be explained in greater detail below, implementations of the present disclosure allow a memory to enter a low power state by instructing a first processing component to avoid accessing a cache, and instructing a second processing component to avoid accessing the memory. The first processing component can have a stutter mode which allows its memory fabric to be temporarily idle (e.g., by exhausting a previously- filled buffer). By having the first processing component avoid the cache, the second processing component can more fully utilize the cache to avoid the memory. During a stutter mode of the first processing component, the memory can enter the low power state even if the second processing component is active, advantageously providing power savings without reducing performance. [0009] In one implementation, a device for entering a low power memory state during a non-idle processor state includes a first processing component, a second processing component, a cache, and a control circuit. The control circuit can be configured to instruct the first processing component to avoid allocating in the cache in response to cache misses, instruct the second processing component to allocate in the cache, and instruct a memory device to enter a low power state in response to an idle state of the memory device. [0010] In some examples, the control circuit is further configured to instruct the first processing component to force evictions from the cache in response to cache hits. The first processing component comprises an activity buffer and is configured to fill the activity buffer to a buffer threshold by accessing the memory device. In some examples, the idle state in the memory device corresponds to the first processing component pausing accesses to the memory device while the activity buffer is exhausted. In some examples, the first processing component corresponds to a display engine and the activity buffer corresponds to a display buffer. [0011] In some examples, the first processing component avoiding allocating to the cache allows the second processing component to allocate a workload of the second processing component in the cache. In some examples, the idle state of the memory device corresponds to the second processing component avoiding accesses to the memory device by having the workload of the second processing component allocated in the cache. In some examples, the idle state of the memory device coincides with an active state of the second processing component. In some examples, the low power state of the memory device corresponds to a self-refresh. In some examples, the control circuit is further configured to instruct the memory device to enter