EP-4735989-A1 - MEMORY CONTROLLER AND MEMORY SYSTEM HANDLING POWER LOSS

Abstract

In certain aspects, a memory system includes a non-volatile memory device, and a memory controller coupled to the non-volatile memory device. The memory controller is configured to generate indicator data based on data to be initially programmed to the non-volatile memory device, and, in response to power loss of the memory system, control transmission of the indicator data to the non-volatile memory device. The indicator data is configured to recover the source data.

Inventors

• LIU, WEILIN

Assignees

• Yangtze Memory Technologies Co., Ltd.

Dates

Publication Date

20260506

Application Date

20240910

Claims (20)

1. A memory system, comprising: a non-volatile memory device; and a memory controller coupled to the non-volatile memory device and configured to: generate indicator data based on source data to be initially programmed to the non-volatile memory device, wherein the indicator data is configured to recover the source data; and in response to power loss of the memory system, control transmission of the indicator data to the non-volatile memory device.
2. The memory system of claim 1, wherein the memory controller is further configured to control initial programming of the source data to the non-volatile memory device to become intermediate data on the non-volatile memory device.
3. The memory system of claim 2, wherein the memory controller is further configured to, in response to power resume of the memory system, retrieve the intermediate data and the indicator data, and recover the source data based on the intermediate data and the indicator data.
4. The memory system of claim 2, wherein the non-volatile memory device is configured to, in response to power resume of the memory system, recover the source data based on the intermediate data and the indicator data, and transmit the recovered data to the memory controller.
5. The memory system of any one of claims 2-4, wherein the non-volatile memory device is further configured to, after the initial programming of the source data, further program the source data to become programmed data.
6. The memory system of any one of claims 1-5, wherein the indicator data comprises a bitmap.
7. The memory system of any one of claims 1-6, wherein a size of the indicator data is smaller than a size of the source data.
8. The memory system of any one of claims 1-7, wherein the memory controller comprises a volatile memory configured to store the indicator data.
9. The memory system of any one of claims 1-8, further comprising a power loss protection (PLP) circuit coupled to the memory controller and the non-volatile memory device and configured to provide power to the memory controller and the non-volatile memory device in response to the power loss of the memory system.
10. The memory system of any one of claims 1-9, wherein the memory controller is configured to control the transmission of the indicator data to the non-volatile memory device only in response to the power loss of the memory system.
11. The memory system of any one of claims 1-10, wherein the non-volatile memory device comprises a NAND Flash memory device.
12. A memory controller, comprising: an interface coupled to a non-volatile memory device; and a processor coupled to the interface and configured to: generate indicator data based on source data to be initially programmed to the non-volatile memory device, wherein the indicator data is configured to recover the source data; and in response to power loss of the memory controller, control transmission of the indicator data to the non-volatile memory device through the interface.
13. The memory controller of claim 12, wherein the processor is configured to control initial programming of the source data to the non-volatile memory device to become intermediate data on the non-volatile memory device through the interface.
14. The memory controller of claim 13, wherein the interface is further configured to, in response to power resume of the memory controller, retrieve the intermediate data and the indicator data from the non-volatile memory device; and the processor is further configured to recover the source data based on the intermediate data and the indicator data.
15. The memory controller of claim 13, wherein the interface is further configured to receive recovered data from the non-volatile memory device; and the source data is recovered by the non-volatile memory device based on the intermediate data and the indicator data in response to power resume of the memory controller.
16. The memory controller of any one of claims 13-15, wherein the processor is further configured to, after the initial programming of the source data, control programming of the source data to the non-volatile memory device to become programmed data on the non-volatile memory device.
17. The memory controller of any one of claims 12-16, wherein the indicator data comprises a bitmap.
18. The memory controller of any one of claims 12-17, wherein a size of the indicator data is smaller than a size of the source data.
19. The memory controller of any one of claims 12-18, further comprising a volatile memory configured to store the indicator data.
20. The memory controller of any one of claims 12-19, wherein the processor is configured to control the transmission of the indicator data to the non-volatile memory device only in response to the power loss of the memory controller.

Description

MEMORY CONTROLLER AND MEMORY SYSTEM HANDLING POWER LOSS BACKGROUND The present disclosure relates to memory devices and operation methods thereof. Flash memory is a low-cost, high-density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR Flash memory and NAND Flash memory. Various operations can be performed by Flash memory, such as read, program (write) , and erase. For NAND Flash memory, an erase operation can be performed at the block level, and a program operation or a read operation can be performed at the page level. SUMMARY In one aspect, a memory system includes a non-volatile memory device, and a memory controller coupled to the non-volatile memory device. The memory controller is configured to generate indicator data based on source data to be initially programmed to the non-volatile memory device, and in response to power loss of the memory system, control transmission of the indicator data to the non-volatile memory device. The indicator data is configured to recover the source data. In some implementations, the memory controller is further configured to control initial programming of the source data to the non-volatile memory device to become intermediate data on the non-volatile memory device. In some implementations, the memory controller is further configured to in response to power resume of the memory system, retrieve the intermediate data and the indicator data, and recover the source data based on the intermediate data and the indicator data. In some implementations, the non-volatile memory device is configured to, in response to power resume of the memory system, recover the source data based on the intermediate data and the indicator data, and transmit the recovered source data to the memory controller. In some implementations, the non-volatile memory device is configured to after the initial programming of the source data, further program the source data to become programmed data. In some implementations, the indicator data includes a bitmap. In some implementations, a size of the indicator data is smaller than a size of the source data. In some implementations, the memory controller includes a volatile memory configured to store the indicator data. In some implementations, the memory system further includes a power loss protection (PLP) circuit coupled to the memory controller and the non-volatile memory device and configured to provide power to the memory controller and the non-volatile memory device in response to the power loss of the memory system. In some implementations, the memory controller is configured to control transmission of the indicator data to the non-volatile memory device only in response to the power loss of the memory system. In some implementations, the non-volatile memory device includes a NAND Flash memory device. In another aspect, a memory controller includes an interface coupled to a non-volatile memory device, and a processor coupled to the interface. The processor is configured to generate indicator data based on source data to be initially programmed to the non-volatile memory device, and in response to power loss of the memory controller, control transmission of the indicator data to the non-volatile memory device through the interface. The indicator data is configured to recover the source data. In some implementations, the processor is configured to control initial programming of the source data to the non-volatile memory device to become intermediate data on the non-volatile memory device through the interface. In some implementations, the interface is further configured to in response to power resume of the memory controller, retrieve the intermediate data and the indicator data from the non-volatile memory device. In some implementations, the processor is further configured to recover the source data based on the intermediate data and the indicator data. In some implementations, the interface is further configured to receive recovered data from the non-volatile memory device. In some implementations, the source data is recovered by the non-volatile memory device based on the intermediate data and the indicator data in response to power resume of the memory controller. In some implementations, the processor is further configured to after the initial programming of the source data, control programming of the source data to the non-volatile  memory device to become programmed data on the non-volatile memory device. In some implementations, the indicator data includes a bitmap. In some implementations, a size of the indicator data is smaller than a size of the source data. In some implementations, the memory controller further includes a volatile memory configured to store the indicator data. In some implementations, the processor is configured to control the transmission of the indicator data to the non-volatile memory device only in response to the power loss of the memory co