EP-4735993-A1 - IMPROVING COVERAGE IN FUNCTIONAL VERIFICATION BY COORDINATED RANDOMIZATION OF VARIABLES ACROSS MULTIPLE CLASSES

Abstract

A description of stimuli used for functional verification of a circuit design is received. The description includes classes of variables and the variable include random variables. A coverage model for the functional verification of the circuit design is also received. The coverage model includes coverage targets that are functions of the variables. A processing device generates stimuli for multiple iterations of the functional verification, as follows. Context values, which include values of the random variables for the stimuli, are maintained. The values of the random variables in an individual class are randomized, and the randomization of the random variables in the individual class is biased to hit the coverage targets given the context values for the random variables outside the individual class. Whether the coverage targets are hit by the generated stimuli is determined.

Inventors

• BISWAS, Parijat
• JAWED, DANISH
• SHARMA, SIDDARTH
• GOPALAN, BADRI

Assignees

• Synopsys, Inc.

Dates

Publication Date

20260506

Application Date

20240620

Claims (20)

1. 1. A method comprising: receiving a description of stimuli used for functional verification of a circuit design, the description comprising classes of variables that include random variables; and receiving a coverage model for the functional verification of the circuit design; the coverage model comprising coverage targets that are functions of the variables; generating, by a processing device, the stimuli for multiple iterations of the functional verification, comprising: maintaining context values comprising values of the random variables for the stimuli; randomizing values of the random variables in an individual class; and biasing the randomization of the random variables in the individual class to hit the coverage targets given the context values for the random variables outside the individual class; and determining whether the coverage targets are hit by the generated stimuli.
2. 2. The method of claim 1, further comprising: maintaining coverage holes data indicating which coverage targets have not yet been hit by previously generated stimuli, wherein randomization of the random variables is biased to hit the unhit coverage targets based on the coverage holes data.
3. 3. The method of claim 1, wherein biasing the randomization of the random variables comprises applying temporary constraints to the randomization of the random variables.
4. 4. The method of claim 1, wherein biasing the randomization of the random variables comprises temporarily modifying a probability distribution for the randomization.
5. 5. The method of claim 1, wherein generating stimuli for multiple iterations of the functional verification further comprises randomizing values of the random variables one class at a time.
6. 6. The method of claim 1, further comprising: based on the coverage model, identifying which coverage targets depend on which random variables.
7. 7. The method of claim 1, wherein the classes are user-defined data types that encapsulate data and functions related to that data.
8. 8. A system comprising a compiler and a verification testbench, wherein: the compiler is configured to: receive a coverage model for functional verification of a circuit design; the coverage model comprising coverage targets that are functions of variables for stimuli used for the functional verification, the variables including random variables; and from the coverage model, determine and store context connectivity information that identifies which coverage targets depend on which random variables; and the verification testbench is configured to perform multiple stages of constrained random verification of the circuit design, each stage for a selected set of coverage targets and for a selected class of variables; each stage comprising: accessing the context connectivity information to identify which random variables the selected set of coverage targets depends on; accessing context values from prior stages for values of random variables outside the selected class; performing multiple iterations of randomizing values of random variables in the selected class, wherein the randomization is biased to hit the coverage targets given the context values for the random variables outside the selected class; and updating the context values.
9. 9. The system of claim 8, wherein performing the multiple stages randomizes values of the random variables one class at a time.
10. 10. The system of claim 9, wherein the multiple stages are performed in parallel.
11. 11. The system of claim 8, wherein the context connectivity information includes one-to- many, one-to-one, and many-to-one dependencies of the coverage targets on the random variables.
12. 12. The system of claim 8, wherein the verification testbench comprises a SystemVerilog constraint solver.
13. 13. The system of claim 12, wherein the random variables outside the selected class are treated as state variables by the SystemVerilog constraint solver.
14. 14. The system of claim 8, wherein the verification testbench includes a database containing the context connectivity information and the context values from prior stages.
15. 15. The system of claim 8, wherein the verification testbench includes a database containing, for each class, the context values for random variables outside the class.
16. 16. The system of claim 8, wherein the verification testbench includes a database containing, for each coverage target, the context values for random variables on which the coverage target depends.
17. 17. A non-transitory computer readable medium comprising stored instructions, which when executed by a processing device, cause the processing device to perform multiple stages of: determining which random variables on which a set of coverage targets depend; wherein the random variables are stimuli for functional verification of a circuit design, and the coverage targets are coverage targets for the functional verification; determining a class of the random variables for randomization during the current stage; retrieving values of random variables that are outside the class; performing multiple iterations of: randomizing values of the random variables in the class, wherein the randomization is biased to hit the coverage targets given the values of the random variables outside the class; and performing the functional verification using the randomized values for the random variables in the class and using the retrieved values for random variables outside the class.
18. 18. The non-transitory computer readable medium of claim 17, wherein the coverage targets include cross-products of random variables in the class with random variables outside the class.
19. 19. The non-transitory computer readable medium of claim 17, wherein the random variables are user-defined and subject to user-defined constraints on values of the random variables.
20. 20. The non-transitory computer readable medium of claim 17, wherein the class is a user- defined data type that encapsulates data and functions related to that data.

Description

IMPROVING COVERAGE IN FUNCTIONAL VERIFICATION BY COORDINATED RANDOMIZATION OF VARIABLES ACROSS MULTIPLE CLASSES Inventors: Parijat Biswas Danish Jawed Siddarth Sharma Badri Gopalan TECHNICAL FIELD [0001] The present disclosure relates to functional verification of circuit designs and, more particularly, to improving the generation of enough stimuli to adequately verify the design. BACKGROUND [0002] Functional verification is a process for determining whether a circuit design functions as intended. Coverage refers to the extent to which different stimuli applied to the circuit design exercise (or cover) the intended or specified functionality. Coverage closure is the process of developing a set of stimuli that covers enough test cases to adequately test the circuit design. [0003] However, one challenge of coverage closure is the ability to generate stimuli that exercise rarely occurring functionality of the circuit. In a constraint-random verification setting, some stimuli are modeled as random variables. The values of these stimuli are randomly selected, leading to a certain distribution of which test cases are exercised. Commonly occurring test cases are hit (exercised) frequently by randomly generated stimuli, and moderately common test cases are hit with moderate frequency. However, some test cases may be hit only rarely. The infrequency of these hits consumes a disproportionate number of processing cycles to reach coverage closure. SUMMARY [0004] In some aspects, a method includes the following. A description of stimuli used for functional verification of a circuit design is received. The description includes classes of variables and the variable include random variables. A coverage model for the functional verification of the circuit design is also received. The coverage model includes coverage targets that are functions of the variables. A processing device generates stimuli for multiple iterations of the functional verification, as follows. Context values, which include values of the random variables for the stimuli, are maintained. The values of the random variables in an individual class are randomized, and the randomization of the random variables in the individual class is biased to hit the coverage targets given the context values for the random variables outside the individual class. Whether the coverage targets are hit by the generated stimuli is determined. [0005] In another aspect, a system includes a compiler and a verification testbench. The compiler receives a coverage model for functional verification of a circuit design. The coverage model includes coverage targets that are functions of variables for stimuli used for the functional verification. The variables include random variables. From the coverage model, the compiler determines and stores context connectivity information that identifies which coverage targets depend on which random variables. The verification testbench performs multiple stages of constrained random verification of the circuit design. Each stage is for a selected set of coverage targets and a selected class of variables. For each stage, the context connectivity information is accessed to identify which random variables the selected set of coverage targets depends on. Context values from prior stages for values of random variables outside the selected class are accessed. The values of random variables in the selected class are randomized for multiple iterations, but the randomization is biased to hit the coverage targets given the context values for the random variables outside the selected class. The context values are updated. [0006] Other aspects include components, devices, systems, improvements, methods, processes, applications, computer readable mediums, and other technologies related to any of the above. BRIEF DESCRIPTION OF THE DRAWINGS [0007] The disclosure will be understood more fully from the detailed description given below and from the accompanying figures of embodiments of the disclosure. The figures are used to provide knowledge and understanding of embodiments of the disclosure and do not limit the scope of the disclosure to these specific embodiments. Furthermore, the figures are not necessarily drawn to scale. [0008] Fig. 1 is a flow diagram for generating test stimuli, in accordance with some embodiments of the present disclosure. [0009] Fig. 2 shows parts of a verification testbench and coverage model, in accordance with some embodiments of the present disclosure. [0010] Figs. 3A and 3B are another flow diagram for generating test stimuli, in accordance with some embodiments of the present disclosure. [0011] Figs. 4A and 4B show experimental results for generating test stimuli, in accordance with some embodiments of the present disclosure. [0012] Fig. 5 depicts a flowchart of various processes used during the design and manufacture of an integrated circuit, in accordance with some embodiments of the present disclosure. [0013] Fig. 6 depicts a