EP-4736017-A1 - MULTI-HOST AND MULTI-CLIENT DIRECT MEMORY ACCESS SYSTEM HAVING A READ SCHEDULER

Abstract

A direct memory access (DMA) system includes a read request circuit configured to receive read requests from a plurality of client circuits. The DMA system includes a response reassembly circuit configured to reorder read completion data received from a plurality of different hosts in response to the read requests. The DMA system includes a read scheduler circuit configured to schedule conveyance of the read completion data from the response reassembly circuit to the plurality of client circuits. The DMA system includes a data pipeline circuit including a plurality of data paths. The plurality of data paths are configured to convey the read completion data as scheduled by the read scheduler circuit to respective ones of the plurality of client circuits.

Inventors

• THYAMAGONDLU, Chandrasekhar, S.
• SHARMA, KUSHAGRA
• KISANAGAR, Surender, Reddy

Assignees

• Xilinx, Inc.

Dates

Publication Date

20260506

Application Date

20240628

Claims (1)

1. 230092-WO-SEC1_8131-0635.1 PATENT CLAIMS What is claimed is: 1. A direct memory access (DMA) system, comprising: a read request circuit configured to receive read requests from a plurality of client circuits; a response reassembly circuit configured to reorder read completion data received from a plurality of hosts in response to the read requests; a read scheduler circuit configured to schedule conveyance of the read completion data from the response reassembly circuit to the plurality of client circuits; and a data pipeline circuit including a plurality of data paths, wherein the plurality of data paths are configured to convey the read completion data as scheduled by the read scheduler circuit to respective ones of the plurality of client circuits. 2. The DMA system of claim 1, wherein the read scheduler circuit implements a credit mode selected from a plurality of different credit modes for a plurality of virtual channels on a per data virtual channel basis. 3. The DMA system of claim 2, wherein the plurality of different credit modes includes a destination credit mode in which the read scheduler circuit maintains a pool of credits for conveyance of read completion data beat-by-beat. 4. The DMA system of claim 2, wherein the plurality of different credit modes includes a notify credit mode in which the read scheduler circuit notifies a selected client circuit of available read completion data for a selected data virtual channel and the selected client circuit issues a dequeue request to the read scheduler circuit for a packet of read completion data. 5. The DMA system of claim 1, wherein each data path of the data pipeline circuit includes an alignment circuit that is configurable to align read completion data prior to sending the read completion data to a selected client circuit of the plurality of client circuits based on a data alignment specified by the selected client circuit. 230092-WO-SEC1_8131-0635.1 PATENT 6. The DMA system of claim 1, wherein the read scheduler circuit comprises: a plurality of first counters including a first counter for each data virtual channel of a plurality of data virtual channels and a plurality of second counters including a second counter for each data virtual channel, wherein the plurality of first counters and the plurality of second counters each count received beats of read completion data on a per data virtual channel basis. 7. The DMA system of claim 6, wherein the plurality of second counters are configured to maintain a count of beats of read completion data to be conveyed to a plurality of client circuits on a per data virtual channel basis. 8. The DMA system of claim 6, wherein the read scheduler circuit comprises: a first arbitration circuit configured to arbitrate among the plurality of data virtual channels corresponding to a plurality of different client circuits, wherein the first arbitration circuit is further configured to issue grants to selected data virtual channels of the plurality of data virtual channels; and wherein first arbitration circuit is configured to arbitrate only among each data virtual channel of the plurality of data virtual channels for which at least one beat of read completion data has been received based on the plurality of first counters. 9. The DMA system of claim 8, wherein first arbitration circuit is configured to decrement one or more first counters of the plurality of first counters by lengths of read requests for the plurality of data virtual channels causing selected ones of the plurality of first counters to have negative values, wherein the selected ones of the plurality of first counters with negative values are not considered for arbitration by the first arbitration circuit. 10. The DMA system of claim 8, wherein the read scheduler circuit comprises: a second arbitration circuit coupled to the first arbitration circuit and configured to arbitrate among the plurality of different client circuits for which grants of data virtual channels have been issued by the first arbitration circuit; and 230092-WO-SEC1_8131-0635.1 PATENT wherein the second arbitration circuit is configured to decrement different ones of the plurality of second counters based on individual beats of read completion data conveyed to the plurality of client circuits. 11. The DMA system of claim 10, wherein the read scheduler circuit comprises: a plurality of third counters configured to count end-of-packet (EOP) read requests that have been committed to different ones of the plurality of hosts for the plurality of data virtual channels. 12. The DMA system of claim 11, wherein the first arbitration circuit is configured to start scheduling conveyance of data for a selected data virtual channel of the plurality of data virtual channels only in response to determining that an EOP read request has been committed for the selected data virtual channel based on the plurality of third counters. 13. A method implemented by a direct memory access system, the method comprising: receiving a plurality of read requests directed to a plurality of hosts, wherein the plurality of read requests are received from a plurality of client circuits conveyed over a plurality of request virtual channels; receiving beats of read completion data for a plurality of data virtual channels in response to the plurality of read requests, wherein the plurality of data virtual channels are allocated among the plurality of request virtual channels; and arbitrating among different ones of the plurality of client circuits for which at least one beat of read completion data has been received and for which an end-of- packet (EOP) read request has been committed to at least one of the plurality of hosts. 14. The method of claim 13, further comprising: implementing a credit mode selected from a plurality of credit modes, wherein the plurality of credit modes control conveyance of beats of read completion data to the plurality of client circuits. 15. The method of claim 13, further comprising: 230092-WO-SEC1_8131-0635.1 PATENT aligning read completion data provided to the plurality of client circuits based on a data alignment specified by respective ones of the plurality of client circuits.

Description

230092-WO-SEC1_8131-0635.1 PATENT MULTI-HOST AND MULTI-CLIENT DIRECT MEMORY ACCESS SYSTEM HAVING A READ SCHEDULER TECHNICAL FIELD [0001] This disclosure relates to integrated circuits (ICs) and, more particularly, to a multi-host and multi-client direct memory access system having a read scheduler circuit. BACKGROUND [0002] Many modern computing environments may include a plurality of host data processing systems (host systems) coupled to one or more peripheral devices. An example of a peripheral device is a hardware accelerator. The host systems may offload tasks to be performed by the peripheral devices. A peripheral device may include a plurality of compute circuits coupled to a direct memory access (DMA) system that facilitates data movement between the host systems and the compute circuits. More particularly, the DMA system facilitates data movement between memory of the host systems that correspond to different processes, functions, and/or applications executing therein and the compute circuits of the peripheral device. The compute circuits, being coupled to the DMA system, are also referred to as “client circuits.” SUMMARY [0003] In one or more example implementations, a direct memory access (DMA) system includes a read request circuit configured to receive read requests from a plurality of client circuits. The DMA system includes a response reassembly circuit configured to reorder read completion data received from a plurality of hosts in response to the read requests. The DMA system includes a read scheduler circuit configured to schedule conveyance of the read completion data from the response reassembly circuit to the plurality of client circuits. The DMA system includes a data pipeline circuit including a plurality of data paths. The plurality of data paths are configured to convey the read completion data as scheduled by the read scheduler circuit to respective ones of the plurality of client circuits. 230092-WO-SEC1_8131-0635.1 PATENT [0004] The foregoing and other implementations can each optionally include one or more of the following features, alone or in combination. Some example implementations include all the following features in combination. [0005] In some aspects, the read scheduler circuit includes an arbitration circuit configured to arbitrate only among each of a plurality of data virtual channels for which at least one beat of read completion data has been received by the response reassembly circuit. [0006] In some aspects, the read scheduler circuit includes a plurality of counters configured to count end-of-packet (EOP) read requests committed to the plurality of hosts for each of a plurality of data virtual channels. [0007] In some aspects, the read scheduler circuit includes an arbitration circuit configured to start scheduling for a selected data virtual channel only in response to determining that an EOP read request has been committed for the selected data virtual channel based on the plurality of counters. [0008] In some aspects, the read scheduler circuit implements a credit mode selected from a plurality of different credit modes on a per data virtual channel basis. [0009] In some aspects, the plurality of different credit modes includes a destination credit mode in which the read scheduler circuit maintains a pool of credits for conveyance of read completion data beat-by-beat. [0010] In some aspects, the plurality of different credit modes include a notify credit mode in which the read scheduler circuit notifies a selected client circuit of available read completion data for a selected data virtual channel and the selected client circuit issues a dequeue request to the read scheduler circuit for a packet of read completion data. [0011] In some aspects, each data path includes an alignment circuit that is configurable to align read completion data prior to sending the read completion data to a selected client circuit of the plurality of client circuits based on a data alignment specified by the selected client circuit. [0012] In some aspects, the read scheduler circuit includes a first arbitration circuit configured to arbitrate among a plurality of data virtual channels corresponding to a plurality of different client circuits. The first arbitration circuit is configured to issue grants to selected data virtual channels of the plurality of data virtual channels. 230092-WO-SEC1_8131-0635.1 PATENT [0013] In some aspects, the read scheduler circuit includes a second arbitration circuit coupled to the first arbitration circuit and configured to arbitrate among the plurality of different client circuits for which grants of data virtual channels have been issued by the first arbitration circuit. [0014] In some aspects, the read scheduler circuit includes a plurality of first counters including a first counter for each data virtual channel and a plurality of second counters including a second counter for each data virtual channel. The plurality of first counters and the pl