EP-4736162-A1 - SYSTEM AND METHOD FOR IMPLEMENTING TEMPERATURE COMPENSATION IN A MEMORY DEVICE

Abstract

A method of operating memory cells includes programming memory cells at a first temperature to different program states associated with first read current values confirmed by using nominal read conditions. Modified read conditions are determined such that a second read current for the one memory cells at a second temperature is approximately equal to the first read current value for the one memory cell. A read operation is performed on the memory cells at the second temperature using the modified read conditions to determine respective third read current values. Error read current values are determined as respective differences between the first and third read current values. Upper and lower program states are assigned to respective desired program states, with read currents that correspond approximately to respective determined error read current values, and are separated approximately by a respective target read current value associated with the respective desired program state.

Inventors

• FESTES, Gilles
• LEMKE, STEVEN
• SCHNEIDER, LOUISA
• OM'MANI, HENRY
• TRAN, HIEU VAN

Assignees

• Silicon Storage Technology, Inc

Dates

Publication Date

20260506

Application Date

20230920

Claims (20)

1. 1. A method of operating a plurality of memory cells, comprising: programming respective ones of the plurality of memory cells while at a first temperature to one of a plurality of different program states, wherein respective ones of the different program states are associated with a corresponding first read current value that is confirmed by performing a first read operation using nominal read conditions; determining modified read conditions using a second read operation for at least one of the memory cells while at a second temperature different than the first temperature, such that a second read current for the one memory cell using the modified read conditions in the second read operation is approximately equal to the first read current value for the one memory cell using the nominal read conditions in the first read operation; performing a third read operation on respective ones of the memory cells while at the second temperature using the modified read conditions to determine respective third read current values for the memory cells; determining error read current values for respective ones of the memory cells, which are the respective differences between the first read current values and the third read current values; and for respective ones of a plurality of desired program states, assigning an upper program state and a lower program state to the desired program state, wherein a read current value for the assigned upper program state and a read current value for the assigned lower program state: correspond approximately to one of the determined error read current values, and are separated approximately by a target read current value associated with the desired program state.
2. 2. The method of claim 1, wherein the second temperature is higher than the first temperature.
3. 3. The method of claim 1, comprising: programming user data that corresponds to one of the desired program states using a first memory cell and a second memory cell of the plurality of memory cells by programming the first memory cell to the upper program state assigned to the desired one of the program states and programming the second memory cell to the lower program state assigned to the desired one of the program states.
4. 4. The method of claim 3, comprising: reading the user data from the first memory cell and the second memory cell in a read operation by: determining a first read current value for the first memory cell using the nominal read conditions, determining a second read current value for the second memory cell using the nominal read conditions, and subtracting the second read current value from the first read current value.
5. 5. The method of claim 4, wherein the subtracting is performed using a differential sense amplifier.
6. 6. The method of claim 1, wherein the programming respective ones of the plurality of memory cells to one of a plurality of different program states comprises programming the one memory cell used for the second read operation to one of the different program states that is a highest program state relative to the different program states programmed to others of the plurality of memory cells.
7. 7. The method of claim 1, comprising: generating a polynomial equation representing the respective differences between the first read current values and the third read current values.
8. 8. The method of claim 7, wherein the assigning the upper program state and the lower program state is performed using the polynomial equation.
9. 9. The method of claim 1, wherein the assigning the upper program states and the lower program states comprises: generating a first polynomial equation representing the upper program states for the plurality of desired program states; generating a second polynomial equation representing the lower program states for the plurality of desired program states; and using the first polynomial equation and the second polynomial equation for the assigning of the upper program states and the lower program states for the desired program states.
10. 10. The method of claim 1, wherein the assigning the upper program states and the lower program states comprises: generating a polynomial equation representing a variable common current that is centered between the read current value of the upper program state and the read current value of the lower program state for respective ones of the desired program states; and using the polynomial equation for the assigning of the upper program states and the lower program states for the desired program states.
11. 11. A memory device, comprising: a plurality of memory cells; and circuitry to: program respective ones of the plurality of memory cells while at a first temperature to one of a plurality of different program states, wherein respective ones of the different program states are associated with a corresponding first read current value that is confirmed by a first read operation using nominal read conditions; determine modified read conditions using a second read operation for at least one of the memory cells while at a second temperature different than the first temperature, such that a second read current for the one memory cell using the modified read conditions in the second read operation is approximately equal to the first read current value for the one memory cell using the nominal read conditions in the first read operation; perform a third read operation on respective ones of the memory cells while at the second temperature using the modified read conditions to determine respective third read current values for the memory cells; determine error read current values for respective ones of the memory cells, which are the respective differences between the first read current values and the third read current values; and for respective ones of a plurality of desired program states, assign an upper program state and a lower program state to the desired program state, wherein a read current value for the assigned upper program state and a read current value for the assigned lower program state: correspond approximately to one of the determined error read current values, and are separated approximately by a target read current value associated with the desired program state.
12. 12. The memory device of claim 11, wherein the second temperature is higher than the first temperature.
13. 13. The memory device of claim 11, wherein the circuitry is to: program user data that corresponds to one of the desired program states using a first memory cell and a second memory cell of the plurality of memory cells including program the first memory cell to the upper program state assigned to the desired one of the program states and program the second memory cell to the lower program state assigned to the desired one of the program states.
14. 14. The memory device of claim 13, wherein the circuitry is to: read the user data from the first memory cell and the second memory cell in a read operation including: determine a first read current value for the first memory cell using the nominal read conditions, determine a second read current value for the second memory cell using the nominal read conditions, and subtract the second read current value from the first read current value.
15. 15. The memory device of claim 14, comprising: a differential sense amplifier for performing the subtracting.
16. 16. The memory device of claim 11, wherein the program of respective ones of the plurality of memory cells to one of a plurality of different program states comprises program the one memory cell used for the second read operation to one of the different program states that is a highest program state relative to the different program states programmed to others of the plurality of memory cells.
17. 17. The memory device of claim 11, wherein the circuitry is to: generate a polynomial equation representing the respective differences between the first read current values and the third read current values.
18. 18. The memory device of claim 17, wherein the circuitry is to: assign the upper program state and the lower program state using the polynomial equation.
19. 19. The memory device of claim 11, wherein the circuitry is to assign the upper program states and the lower program states including: generate a first polynomial equation representing the upper program states for the plurality of desired program states; generate a second polynomial equation representing the lower program states for the plurality of desired program states; and use the first polynomial equation and the second polynomial equation to assign the upper program states and the lower program states for the desired program states.
20. 20. The memory device of claim 11, wherein the circuitry is to assign the upper program states and the lower program states including: generate a polynomial equation representing a variable common current that is centered between the read current value of the upper program state and the read current value of the lower program state for respective ones of the desired program states; and use the polynomial equation to assign the upper program states and the lower program states for the desired program states.

Description

SYSTEM AND METHOD FOR IMPLEMENTING TEMPERATURE COMPENSATION IN A MEMORY DEVICE RELATED APPLICATION [0001] This application claims the benefit of U.S. Patent Application No. 18/367,921, filed on September 13, 2023. FIELD OF THE INVENTION [0002] The present invention relates to non-volatile memory arrays. BACKGROUND OF THE INVENTION [0003] Memory devices with split gate non-volatile memory cells, and arrays of such cells, are well known. For example, U.S. Patent 5,029,130 (“the ’ 130 patent”) discloses an array of split gate non-volatile memory cells. The memory cell is shown in Fig. 1. Each memory cell 10 includes source and drain regions 14/16 formed in a semiconductor substrate 12, with a channel region 18 there between. A floating gate 20 is formed over and insulated from (and controls the conductivity of) a first portion of the channel region 18, and over a portion of the drain region 16. A control gate 22 (also referred to a word line gate or select gate) has a first portion 22b that is disposed over and insulated from (and controls the conductivity of) a second portion of the channel region 18, and a second portion 22c that extends up and over the floating gate 20. The floating gate 20 and control gate 22 are insulated from the substrate 12 by a gate oxide 26. [0004] The memory cell is erased (where electrons are removed from the floating gate) by placing a high positive voltage on the control gate 22, which causes electrons on the floating gate 20 to tunnel through the intermediate insulation (e.g., a tunnel oxide) 24 from the floating gate 20 to the control gate 22 via Fowler-Nordheim tunneling. [0005] The memory cell is programmed (where electrons are placed on the floating gate) by placing a positive voltage on the control gate 22, and a positive voltage on the drain 16. Electron current will flow from the source 14 towards the drain 16. The electrons will accelerate and become heated when they reach the gap between the control gate 22 and the floating gate 20. Some of the heated electrons will be injected through the gate oxide 26 onto the floating gate 20 due to the attractive electrostatic force from the floating gate 20. [0006] The memory cell is read by placing positive read voltages on the drain 16 and control gate 22 (which turns on the channel region under the control gate). If the floating gate 20 is positively charged (i.e. erased of electrons and positively coupled to the drain 16), then the portion of the channel region under the floating gate 20 is turned on as well, and current will flow across the channel region 18, which is sensed as the erased or “1” state. If the floating gate 20 is negatively charged (i.e. programmed with electrons), then the portion of the channel region under the floating gate 20 is mostly or entirely turned off, and current will not flow (or there will be little flow) across the channel region 18, which is sensed as the programmed or “0” state. [0007] The architecture of the memory array is shown in Fig. 2. The memory cells 10 are arranged in rows and columns. In each column, the memory cells are arranged end to end in mirror fashion, so that they are formed as pairs of memory cells each sharing a common source region 14 (S), and each adjacent set of memory cell pairs sharing a common drain region 16 (D). All the source regions 14 (S) for any given row of memory cells are electrically connected together by a source line 14a. Optionally, a group of the source lines 14a, or all the source lines 14a in the memory array, can be electrically connected together by a common source line 14b. All the drain regions 16 (D) for any given column of memory cells are electrically connected together by a bit line 16a. All the control gates 22 for any given row of memory cells are electrically connected together by a control gate line 22a (also called word lines or select gate lines). Therefore, while the memory cells can be individually programmed and read, memory cell erasure is performed row by row (each row of memory cells is erased together, by the application of a high voltage on the control gate line 22a). Row and column decoders decode incoming row and column addresses and provide the appropriate voltages to the control gate lines 22a and bit lines 16a, respectively. A sense amplifier senses the voltages or currents on the bit lines during read operations. [0008] Those skilled in the art understand that the source and drain can be interchanged, where the floating gate can extend partially over the source instead of the drain, as shown in Fig. 3. Fig. 4 best illustrates the corresponding memory cell architecture, including the memory cells 10, the source lines 14a, the bit lines 16a, and the control gate lines 22a. As is evident from the figures, memory cells 10 of the same row share the same source line 14a and the same control gate line 22a, while the drains of all cells of the same column are electrically connected to the same bit line 16a. The array design permi