EP-4736163-A1 - RELIABILITY IMPROVEMENTS USING MEMORY DIE BINNING

Abstract

A processing device analyzes one or more property and capability characteristics of a plurality of memory devices produced in a development process executed by a memory device development system and identifies respective subsets of the plurality of memory devices having property and capability characteristics that meet respective standards associated with a plurality of different use cases. The processing device further allocates the respective subsets to groups of memory devices corresponding to the different use cases.

Inventors

• TAI, Ying Yu
• WAN, JUN
• JEON, SEUNGJUNE
• ZHOU, Zhenming
• ZHU, JIANGLI

Assignees

• Micron Technology, Inc.

Dates

Publication Date

20260506

Application Date

20240625

Claims (20)

1. 1. A system comprising: a memory device development system to execute a development process to produce a plurality of memory devices; and a processing device, operatively coupled with the memory device development system, to perform operations comprising: analyzing one or more property and capability characteristics of the plurality of memory devices produced in the development process; identifying respective subsets of the plurality of memory devices having property and capability characteristics that meet respective standards associated with a plurality of different use cases; and allocating the respective subsets to groups of memory devices corresponding to the different use cases.
2. 2. The system of claim 1, wherein the one or more property and capability characteristics comprise a read window budget (RWB) of the plurality of memory devices.
3. 3. The system of claim 1, wherein the one or more property and capability characteristics comprise one or more of endurance, data retention capability, read disturb tolerance, latent read disturb tolerance, a number of blocks/pages available to a user, or a number of bitlines/columns available to the user of the plurality of memory devices.
4. 4. The system of claim 1, wherein the respective standards associated with the plurality of different use cases comprise a respective minimum level of properties and capabilities associated with each of the plurality of different uses cases.
5. 5. The system of claim 1, wherein the plurality of different uses cases comprise one or more of client systems, mobile applications, enterprise data centers, automotive applications, industry systems, or removable storage devices.
6. 6. The system of claim 1, wherein the development process comprises a plurality of stages, and wherein memory devices produced at each stage have improved property and capability characteristics relative to a previous stage.
7. 7. The system of claim 1, wherein the processing device is to perform operations further comprising: configuring a memory sub-system controller of a memory sub-system comprising one or more of the plurality of memory devices to utilize one or more redundant bitlines of the one or more of the plurality of memory devices to store additional parity data.
8. 8. The system of claim 1, wherein the processing device is to perform operations further comprising: configuring a memory sub-system controller of a memory sub-system comprising one or more of the plurality of memory devices to utilize an adaptive media scan threshold for the one or more of the plurality of memory devices.
9. 9. A method comprising: analyzing one or more property and capability characteristics of a plurality of memory devices produced in a development process executed by a memory device development system; identifying respective subsets of the plurality of memory devices having property and capability characteristics that meet respective standards associated with a plurality of different use cases; and allocating the respective subsets to groups of memory devices corresponding to the different use cases.
10. 10. The method of claim 9, wherein the one or more property and capability characteristics comprise a read window budget (RWB) of the plurality of memory devices.
11. 11. The method of claim 9, wherein the one or more property and capability characteristics comprise one or more of endurance, data retention capability, read disturb tolerance, latent read disturb tolerance, a number of blocks/pages available to a user, or a number of bitlines/columns available to the user of the plurality of memory devices.
12. 12. The method of claim 9, wherein the respective standards associated with the plurality of different use cases comprise a respective minimum level of properties and capabilities associated with each of the plurality of different uses cases.
13. 13. The method of claim 9, wherein the plurality of different uses cases comprise one or more of client systems, mobile applications, enterprise data centers, automotive applications, industry systems, or removable storage devices.
14. 14. The method of claim 9, wherein the development process comprises a plurality of stages, and wherein memory devices produced at each stage have improved property and capability characteristics relative to a previous stage.
15. 15. The method of claim 9, further comprising: configuring a memory sub-system controller of a memory sub-system comprising one or more of the plurality of memory devices to utilize one or more redundant bitlines of the one or more of the plurality of memory devices to store additional parity data.
16. 16. The method of claim 9, further comprising: configuring a memory sub-system controller of a memory sub-system comprising one or more of the plurality of memory devices to utilize an adaptive media scan threshold for the one or more of the plurality of memory devices.
17. 17. Anon-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: analyzing one or more property and capability characteristics of a plurality of memory devices produced in a development process executed by a memory device development system; identifying respective subsets of the plurality of memory devices having property and capability characteristics that meet respective standards associated with a plurality of different use cases; and allocating the respective subsets to groups of memory devices corresponding to the different use cases.
18. 18. The non-transitory computer-readable storage medium of claim 17, wherein the respective standards associated with the plurality of different use cases comprise a respective minimum level of properties and capabilities associated with each of the plurality of different uses cases, and wherein the plurality of different uses cases comprise one or more of client systems, mobile applications, enterprise data centers, automotive applications, industry systems, or removable storage devices.
19. 19. The non-transitory computer-readable storage medium of claim 17, wherein the instructions cause the processing device to perform operations further comprising: configuring a memory sub-system controller of a memory sub-system comprising one or more of the plurality of memory devices to utilize one or more redundant bitlines of the one or more of the plurality of memory devices to store additional parity data.
20. 20. The non-transitory computer-readable storage medium of claim 17, wherein the instructions cause the processing device to perform operations further comprising: configuring a memory sub-system controller of a memory sub-system comprising one or more of the plurality of memory devices to utilize an adaptive media scan threshold for the one or more of the plurality of memory devices.

Description

RELIABILITY IMPROVEMENTS USING MEMORY DIE BINNING TECHNICAL FIELD [001] Embodiments of the disclosure relate generally to memory sub-systems, and more specifically, relate to reliability improvements using memory die binning in the production of memory sub-systems. BACKGROUND [002] A memory sub-system can include one or more memory devices that store data. The memory devices can be, for example, non-volatile memory devices and volatile memory devices. In general, a host system can utilize a memory sub-system to store data at the memory devices and to retrieve data from the memory devices. BRIEF DESCRIPTION OF THE DRAWINGS [003] The present disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure. [004] FIG. 1A is a block diagram illustrating a memory device development system in accordance with some embodiments of the present disclosure. [005] FIG. IB illustrates a timeline for a memory device development process in accordance with some embodiments of the present disclosure. [006] FIG. 1C illustrates a plot of the number of produced memory devices having a certain level of property and capability characteristics in accordance with some embodiments of the present disclosure. [007] FIG. 2 illustrates an example computing system that includes a memory subsystem in accordance with some embodiments of the present disclosure. [008] FIG. 3 is a flow diagram of an example method of using memory die binning in the production of memory sub-systems to improve reliability in accordance with some embodiments of the present disclosure. [009] FIG. 4 is a flow diagram of an example method of utilizing redundant columns on a memory device to improve the error correction capability in a memory sub-system in accordance with some embodiments of the present disclosure. [0010] FIG. 5 is a flow diagram of an example method of utilizing adaptive media scan thresholds to improve the latent read disturb tolerance in a memory sub-system in accordance with some embodiments of the present disclosure. [0011] FIG. 6 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION [0012] Aspects of the present disclosure are directed to reliability improvements using memory die binning in the production of memory sub-systems. A memory sub-system can be a storage device, a memory module, or a hybrid of a storage device and memory module. Examples of storage devices and memory modules are described below in conjunction with FIG. 2. In general, a host system can utilize a memory sub-system that includes one or more components, such as memory devices that store data. The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory subsystem. [0013] A memory sub-system can include high density non-volatile memory devices where retention of data is desired when no power is supplied to the memory device. For example, NAND memory, such as 3D flash NAND memory, offers storage in the form of compact, high density configurations. A non-volatile memory device is a package of one or more dice, each including one or more planes. For some types of non-volatile memory devices (e.g., NAND memory), each plane includes of a set of physical blocks. Each block includes of a set of pages. Each page includes of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell can store one or more bits of binary information, and has various logic states that correlate to the number of bits being stored. The logic states can be represented by binary values, such as “0” and “2”, or combinations of such values. [0014] A memory device can be made up of bits arranged in a two-dimensional or a three-dimensional grid. Memory cells are formed onto a silicon wafer in an array of columns (also hereinafter referred to as bitlines) and rows (also hereinafter referred to as wordlines). A wordline can refer to one or more rows of memory cells of a memory device that are used with one or more bitlines to generate the address of each of the memory cells. The intersection of a bitline and wordline constitutes the address of the memory cell. A block hereinafter refers to a unit of the memory device used to store data and can include a group of memory cells, a wordline group, a wordline, or individual memory cells. One or more blocks can be grouped together to form separate partitions (e.g., planes) of the memory device in order to allow concurrent operations to take place on each plane. [0015] One example of a memory sub-system is a solid-state drive (SSD) that includes one or more non-volatile memory devices (e.g., memory dies) and a memory sub-system controller to manage the non-volatile memory devices. The memory sub-systems can ultimately be sold to a variety of different customers and/or be