EP-4736164-A1 - HOST-TO-DEVICE INTERFACE CIRCUITRY TESTING

Abstract

Some implementations provide systems methods and devices for integrated circuit self-test. The integrated circuit includes interface circuitry configured to read test data and to write the test data into memory of the integrated circuit. The integrated circuit also includes test circuitry configured to test the interface circuitry based on the test data written into memory of the integrated circuit. Some implementations provide an integrated circuit configured for storing and reading data. The integrated circuit includes circuitry configured to write or read a first portion of data to or from a first memory via BIST circuitry of the first memory until a first BIST counter saturates. The integrated circuit also includes circuitry configured to write or read a second portion of the data to or from a second memory via BIST circuitry of the second memory until a second BIST counter saturates.

Inventors

• PATEL, NEHAL

Assignees

• Advanced Micro Devices, Inc.

Dates

Publication Date

20260506

Application Date

20240611

Claims (20)

1. 1 . An integrated circuit configured for self-test, comprising: interface circuitry configured to read test data and to write the test data into memory of the integrated circuit; and test circuitry configured to test the interface circuitry based on the test data written into the memory of the integrated circuit.
2. 2. The integrated circuit of claim 1 , wherein the interface circuitry is configured to read the test data from an external storage device.
3. 3. The integrated circuit of claim 1 , wherein the memory of the integrated circuit comprises a plurality of memories, wherein the plurality of memories are on a same die as the integrated circuit, are within a same package as the integrated circuit, or are both on a same die as the integrated circuit and within a same package as the integrated circuit.
4. 4. The integrated circuit of claim 1 , wherein the memory of the integrated circuit comprises a memory pool.
5. 5. The integrated circuit of claim 1 , wherein the memory of the integrated circuit comprises a plurality of memories, wherein the plurality of memories are configured to be accessed serially, are configured to be written to and read from via built-in self-test (BIST) circuitry, or are both configured to be accessed serially and configured to be written to and read from via BIST circuitry.
6. 6. The integrated circuit of claim 1 , wherein the memory comprises a first memory and a second memory; and wherein the interface circuitry is configured to write a first portion of the test data into the first memory on the integrated circuit until the first portion of the test data has been entirely written to the first memory, and, after the first portion of the test data has been entirely written, to write a second portion of the test data into the second memory on the integrated circuit.
7. 7. The integrated circuit of claim 1 , wherein the memory comprises a first memory and a second memory; and wherein the test circuitry is configured to read a first portion of the test data from the first memory on the integrated circuit until the first portion of the test data has been entirely read from the first memory, and, after the first portion of the test data has been entirely read, reading a second portion of the test data from the second memory on the integrated circuit.
8. 8. The integrated circuit of claim 1 , wherein the test circuitry is configured to read the test data from the memory of the integrated circuit, input the test data to the interface circuitry to generate test output data, and to compare the test output data to expected output data.
9. 9. A method for testing an integrated circuit, the method comprising: writing test data into memory of the integrated circuit over interface circuitry of the integrated circuit; and testing the interface circuitry based on the test data written into the memory of the integrated circuit.
10. 10. The method of claim 9, wherein the test data is written into the memory on the integrated circuit over the interface circuitry of the integrated circuit from an external storage device.
11. 11. The method of claim 9, wherein the memory of the integrated circuit comprises a plurality of memories, wherein the plurality of memories are on a same die as the integrated circuit, are within a same package as the integrated circuit, or are both on a same die as the integrated circuit and within a same package as the integrated circuit.
12. 12. The method of claim 9, wherein the memory of the integrated circuit comprises a memory pool.
13. 13. The method of claim 9, wherein the memory of the integrated circuit comprises a plurality of memories, wherein the plurality of memories are configured to be accessed serially, are configured to be written to and read from via built-in self-test (BIST) circuitry, or are both configured to be accessed serially and configured to be written to and read from via BIST circuitry.
14. 14. The method of claim 9, wherein writing the test data into the memory on the integrated circuit over the interface circuitry comprises writing a first portion of the test data into a first memory on the integrated circuit until the first portion of the test data has been entirely written to the first memory, and, after the first portion of the test data has been entirely written, writing a second portion of the test data into a second memory on the integrated circuit until the second portion of the test data has been entirely written to the second memory.
15. 15. The method of claim 9, wherein testing the interface circuitry based on the test data comprises reading a first portion of the test data into a first memory on the integrated circuit until the first portion of the test data has been entirely read from the first memory, and, after the first portion of the test data has been entirely read, reading a second portion of the test data from a second memory on the integrated circuit until the second portion of the test data has been entirely read from the second memory.
16. 16. The method of claim 9, wherein testing the interface circuitry based on the test data written into the memory of the integrated circuit comprises reading the test data from the memory of the integrated circuit, inputting the test data to the interface circuitry to generate test output data, and comparing the test output data to expected output data.
17. 17. An integrated circuit configured for storing data, comprising: circuitry configured to write a first portion of data to a first memory via built-in self-test (BIST) circuitry of the first memory until a first BIST counter saturates; and circuitry configured to write a second portion of the data to a second memory via BIST circuitry of the second memory until a second BIST counter saturates.
18. 18. The integrated circuit of claim 17, further comprising circuitry configured to trigger writing of the second portion of the data to the second memory based on saturation of the first BIST counter.
19. 19. The integrated circuit of claim 17, wherein the first memory and the second memory are comprised of the integrated circuit or an integrated circuit die, and the integrated circuit comprises circuitry configured to read the data from a memory device that is external to the integrated circuit or to the integrated circuit die.
20. 20. The integrated circuit of claim 17, wherein the first memory and the second memory are comprised of an integrated circuit package, and the integrated circuit comprises circuitry configured to read the data from a memory device that is external to the integrated circuit package.

Description

HOST-TO-DEVICE INTERFACE CIRCUITRY TESTING CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application claims priority to pending U.S. Non-Provisional Patent Application Number 18/343,377, entitled “HOST-TO-DEVICE INTERFACE CIRCUITRY TESTING,” filed on June 28, 2023, the entirety of which is hereby incorporated herein by reference. BACKGROUND [0002] Modern integrated circuits (ICs) are enormously complex, and are typically manufactured in large quantities, with a low tolerance for defects. Accordingly, to promote an acceptably low defect rate, modem ICs are designed to be tested automatically using automatic test equipment (ATE). ATE will typically input test data to the IC and compare the data output in response to the test data to expected output data. If the data output in response to the test data does not match the expected output data, the IC may be defective in some way. BRIEF DESCRIPTION OF THE DRAWINGS [0003] A more detailed understanding can be had from the following description, given by way of example in conjunction with the accompanying drawings wherein: [0004] Figure 1 is a block diagram of an example device in which one or more features of the disclosure can be implemented; [0005] Figure 2 is a block diagram of the device of Figure 1 , illustrating additional detail; [0006] Figure 3 is a block diagram of an example automatic test scenario based on ATE testing; [0007] Figure 4 is a block diagram of another example automatic test scenario based on on-device testing; [0008] Figure 5 is a block diagram of another example automatic test scenario based on on-device testing; [0009] Figure 6 is a flow chart illustrating an example method for automatic test of an IC using an onboard microcontroller; [0010] Figure 7 is a flow chart illustrating an example method for automatic test of an IC using an onboard microcontroller; [0011] Figure 8 is a block diagram illustrating an example memory; [0012] Figure 9 is a block diagram illustrating an example memory with additional components for conducting a built-in-self-test (BIST); [0013] Figure 10 is a block diagram illustrating an example memory pool; [0014] Figure 11 is a block diagram illustrating write operations where write data fills the memory pool shown and described with respect to Figure 10; [0015] Figure 12 is another block diagram illustrating write operations where write data fills the memory pool shown and described with respect to Figure 10; [0016] Figure 13 is another block diagram illustrating write operations where write data fills the memory pool shown and described with respect to Figure 10; [0017] Figure 14 is another block diagram illustrating write operations where write data fills the memory pool shown and described with respect to Figure 10; [0018] Figure 15 is a block diagram illustrating read operations where read data is read from the memory pool shown and described with respect to Figure 10; [0019] Figure 16 is a block diagram illustrating read operations where read data is read from the memory pool shown and described with respect to Figure 10; [0020] Figure 17 is a block diagram illustrating read operations where read data is read from the memory pool shown and described with respect to Figure 10; [0021] Figure 18 is a block diagram illustrating read operations where read data is read from the memory pool shown and described with respect to Figure 10; [0022] Figure 19 is a flow chart illustrating an example method for writing to a memory pool. [0023] Figure 20 is a flow chart illustrating the example method for reading from a memory pool. DETAILED DESCRIPTION [0024] ATE typically inputs test data to an IC under test via a communications interface. The test data is also referred to as a stimulus, test pattern, or scan pattern, in some cases. Some example input interfaces include Peripheral Component Interconnect Express (PCIe) and Universal Serial Bus (USB), however any suitable interface is usable in different implementations. The ATE includes circuitry which implements the interface for communication with circuitry which implements the interface on the IC. Circuitry on the IC (e.g., a scan chain) responds to the input test data, and generates an output to the ATE. The ATE compares the output to an expected output to determine whether the IC is defective. In prior systems, it may be impossible to test the interface circuitry on the IC, e.g., because it is actively receiving the test pattern from the ATE and unavailable for testing. Accordingly, it may be desired to provide systems, methods, and/or devices which address this. [0025] Some implementations provide an integrated circuit configured for selftest. The integrated circuit includes interface circuitry configured to read test data and to write the test data into memory of the integrated circuit. The integrated circuit also includes test circuitry configured to test the interface circuitry based on the test data written into memory of the integrated circuit. [0026] In