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EP-4736204-A1 - INTEGRATED CIRCUITS WITH CAPACITORS

EP4736204A1EP 4736204 A1EP4736204 A1EP 4736204A1EP-4736204-A1

Abstract

A component comprises a substrate comprising a first side and a second side opposite to the first side. A first dielectric layer is formed on the first side, and a plurality of electrically conductive pads extend through the first dielectric layer. A second dielectric layer is formed on the second side, and a plurality of electrically conductive pads extend through the second dielectric layer. A plurality of capacitors are each formed in an opening that extends at least partially from the first side towards the second side of the substrate. Each of the capacitors comprises at least three electrodes. At least one of the plurality of capacitors is coupled on the first side to an electrically conductive pad of the first dielectric layer and is coupled on the second side to an electrically conductive pad of the second dielectric layer.

Inventors

  • KATKAR, RAJESH
  • HABA, BELGACEM

Assignees

  • Adeia Semiconductor Bonding Technologies Inc.

Dates

Publication Date
20260506
Application Date
20240628

Claims (20)

  1. 1. A component comprising: a substrate comprising a first side and a second side opposite to the first side; a first dielectric layer formed on the first side and comprising a plurality of electrically conductive pads extending through the first dielectric layer; a second dielectric layer formed on the second side and comprising a plurality of electrically conductive pads extending through the second dielectric layer; and a plurality of capacitors, each of the capacitors comprising at least three electrodes and formed in an opening that extends at least partially from the first side towards the second side of the substrate, wherein at least one of the plurality of capacitors is coupled on the first side to a first electrically conductive pad of the first dielectric layer and is coupled on the second side to a second electrically conductive pad of the second dielectric layer.
  2. 2. The component of claim 1, further comprising: a first integrated circuit device attached to the first dielectric layer and electrically coupled to at least one of the electrically conductive pads of the first dielectric layer.
  3. 3. The component of claim 1, wherein: a first of the at least three electrodes of a first capacitor of the plurality of capacitors is coupled to ground and the second and third of the at least three electrodes are coupled to power; and a first of the at least three electrodes of a second capacitor of the plurality of capacitors is coupled to power and the second and third of the at least three electrodes are coupled to ground.
  4. 4. The component of claim 3, wherein: at least one of the plurality of capacitors comprises a first conductive layer, a second conductive layer, and a plurality of dielectric layers separating the first and second conductive layers; and the first conductive layer is coupled to a first electrically conductive pad of the first dielectric layer forming the first electrode and the second conductive layer is coupled to a second electrically conductive pad of the first dielectric layer forming the second electrode.
  5. 5. The component of claim 4, wherein the first dielectric layer is a redistribution layer further comprising a plurality of conductive layers formed in the first dielectric layer, the plurality of conductive layers electrically coupling at least a group of the plurality of capacitors to each other.
  6. 6. The component of claim 5, wherein at least a group of the plurality of conductive layers formed in the first dielectric layer comprises: a third conductive layer electrically coupling the first conductive layer of each capacitor of the group; and a fourth conductive layer electrically coupling the second conductive layer of each capacitor of the group.
  7. 7. The component of claim 4, wherein the outermost conductive layer of each capacitor comprises either the first conductive layer or the second conductive layer, and wherein the outermost conductive layer of each capacitor is coupled to a first electrically conductive pad of the second dielectric layer forming the third electrode of the capacitor.
  8. 8. The component of claim 7, wherein the first conductive layer is capable of carrying power and wherein the second conductive layer is capable of carrying ground.
  9. 9. The component of claim 1, further comprising a via formed in the substrate, wherein the via comprises a conductive layer and the conductive layer is coupled to a third electrically conductive pad extending through the first dielectric layer and a second electrically conductive pad extending through the second dielectric layer.
  10. 10. The component of claim 8, wherein the conductive layer is capable of carrying a signal.
  11. 11. The component of claim 1, wherein the plurality of capacitors are coupled to one of the electrically conductive pads of the second dielectric layer.
  12. 12. The component of claim 1, further comprising: an integrated circuit device attached to the second dielectric layer and electrically coupled to at least one of the electrically conductive pads of the second dielectric layer, wherein the second dielectric layer is a redistribution layer further comprising a plurality of conductive layers formed in the second dielectric layer, the plurality of conductive layers electrically coupling at least a group of the plurality of capacitors to each other and forming the third electrode of each capacitor of the group.
  13. 13. The component of claim 2, further comprising: a hybrid bonding interface formed directly between the first dielectric layer and the first integrated circuit device.
  14. 14. The component of claim 1, wherein the substrate is amorphous or crystalline.
  15. 15. The component of claim 1, wherein the plurality of capacitors comprise pass-through capacitors.
  16. 16. A method of forming a plurality of capacitors, the method comprising: forming a plurality of openings on a first side of a substrate, the substrate comprising the first side and a second side opposite the first side; patterning a capacitor in each of the plurality of openings, each capacitor comprising at least three electrodes; etching a portion of the second side of the substrate to reveal a portion of each of the capacitors; forming a first dielectric layer on the first side of the substrate, the first dielectric layer comprising a first plurality of electrically conductive pads extending through the first dielectric layer and coupled to the capacitors; and forming a second dielectric layer on the second side of the substrate, the second dielectric layer comprising a second plurality of electrically conductive pads extending through the second dielectric layer and coupled to the capacitors.
  17. 17. The method of claim 16, further comprising: a first of the at least three electrodes of a first capacitor of the plurality of capacitors is coupled to ground and the second and third of the at least three electrodes are coupled to power; and a first of the at least three electrodes of a second capacitor of the plurality of capacitors is coupled to power and the second and third of the at least three electrodes are coupled to ground.
  18. 18. The method of claim 17, further comprising: forming a first conductive layer, a second conductive layer, and a plurality of dielectric layers separating the first and second conductive layers in each of the plurality of capacitors; coupling the first conductive layer to a first electrically conductive pad of the first dielectric layer forming the first electrode; and coupling the second conductive layer to a second electrically conductive pad of the first dielectric layer forming the second electrode.
  19. 19. The method of claim 18, further comprising forming a plurality of conductive layers in the first dielectric layer, the plurality of conductive layers electrically coupling the plurality of capacitors to each other.
  20. 20. The method of claim 19, wherein forming the plurality of conductive layers in the first dielectric layer further comprises: forming a third conductive layer electrically coupling the first conductive layer of each capacitor; and forming a fourth conductive layer electrically coupling the second conductive layer of each capacitor.

Description

INTEGRATED CIRCUITS WITH CAPACITORS Cross-Reference to Related Application [0001] This application claims the benefit of U.S. Provisional Patent Application No. 63/511,633, filed June 30, 2023, which is hereby incorporated by reference in its entirety. Field [0002] The present disclosure generally relates to semiconductor device manufacturing and assembly and, more particularly, to integrated circuits formed with capacitors and methods of forming the integrated circuits. Summary [0003] Embodiments herein include integrated circuits formed with capacitors, and methods of forming thereof. In some embodiments, the integrated circuits (e.g., passive or active) include a plurality of capacitors, each of which comprises three electrodes. In some embodiments, each capacitor may comprise at least three electrodes. In some embodiments, each capacitor may comprise three or more electrodes. [0004] In some embodiments, a component for a plurality of capacitors each comprising at least three electrodes is provided. The component comprises a substrate comprising a first side and a second side opposite to the first side. A first dielectric layer is formed on the first side and comprises a plurality of electrically conductive pads extending through the first dielectric layer. A second dielectric layer is formed on the second side and comprises a plurality of electrically conductive pads extending through the second dielectric layer. The component comprises a plurality of capacitors which are each formed in an opening or a cavity that extends at least partially from the first side of the substrate towards the second side of the substrate. In some embodiments, the component comprises a plurality of capacitors which are each formed in an opening that extends from the first side of the substrate to the second side of the substrate. At least one of the plurality of capacitors is coupled on the first side to an electrically conductive pad of the first dielectric layer and is coupled to on the second side to an electrically conductive pad of the second dielectric layer. In some embodiments, the plurality of capacitors comprise pass-through capacitors. [0005] In some embodiments, an integrated circuit device (e.g., a passive or an active chip) is attached to the first dielectric layer of the component. The integrated circuit device may be electrically coupled to at least one of the electrically conductive pads of the first dielectric layer. [0006] In some embodiments, the capacitors can directly provide access to power and ground or positive and negative voltage through the electrically conductive pads in the second dielectric layer and directly provide the power and ground or positive and negative voltage to the component to the integrated circuit device, which may remove the need for separate ground vias and power vias (e.g., in another portion of the substrate). Advantageously, the size of large arrays of capacitors (e.g., massive capacitors) can be reduced. By directly accessing power or ground, the distance that power or ground has to travel to the capacitor (and/or the integrated circuit device) may be reduced, thereby reducing impedance in large arrays of capacitors. Each of the plurality of capacitors can be coupled to a distinct power or ground connection, thereby providing an arrangement where each of the capacitors can carry varying voltages which allows for multiple voltage regions to be present in massive capacitors. This may enable a massive capacitor that can provide capacitance to a plurality of integrated circuit devices with different power and ground requirements. [0007] In some embodiments, the first dielectric layer can be a redistribution layer further comprising a plurality of conductive layers formed in the first dielectric layer. The plurality of conductive layers or at least a group of the plurality of conductive layers may electrically couple the plurality of capacitors or at least a group of the plurality of capacitors to each other. This may provide improved distribution of power and ground to and from each of the plurality of capacitors or at least the group of the plurality of capacitors, thereby reducing overall impedance in the massive capacitor. [0008] In some embodiments, the plurality of conductive layers of the redistribution layer may be patterned to electrically couple groups of capacitors to each other. In some embodiments, the redistribution layer may further comprise fuse or anti-fuse components to electrically couple or separate groups of capacitors. The fuse or anti-fuse component may be used to electrically couple or separate groups of capacitors post-manufacturing. This may enable generating capacitors with having particular effective capacitances (e.g., groups of capacitors has effective capacitance as the sum of individual capacitances). [0009] In some embodiments, the plurality of capacitors may be coupled to one of the electrically conductive pads of the second dielectric layer.