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EP-4736222-A1 - PACKAGING ARCHITECTURE FOR WAFER-SCALE KNOWN-GOOD-DIE HYBRID BONDING

EP4736222A1EP 4736222 A1EP4736222 A1EP 4736222A1EP-4736222-A1

Abstract

Disclosed herein are microelectronic assemblies, related apparatuses, and methods. In some embodiments, a microelectronic assembly may include a first die in a first layer; and a second and third die in a second layer, the second layer coupled to the first layer by hybrid bond interconnects having a first pad and a second pad, wherein the first pad is coupled to a first via in the second die and the first pad is offset from the first via by a first dimension, and the second pad is coupled to a second via in the third die and the second pad is offset from the second via by a second dimension different than the first dimension. In some embodiments, the first pad is offset from the first via in a first direction and the second pad is offset from the second via in a second direction different than the first direction.

Inventors

  • KARHADE, OMKAR G.
  • KRISHNATREYA, Bhaskar Jyoti
  • SURAPANENI, RAJESH
  • BRUN, XAVIER FRANCOIS
  • KILAMBI, HARINI
  • JUN, Kimin
  • ELSHERBINI, Adel A.
  • MATTHIESEN, John Edward Zeug
  • WIDODO, TRIANGGONO
  • DAS, Adita
  • BHATIA, MOHIT
  • ANTARTIS, Dimitrios

Assignees

  • INTEL Corporation

Dates

Publication Date
20260506
Application Date
20231027

Claims (20)

  1. 1. A microelectronic assembly, comprising: a first die in a first layer; and a second die and a third die in a second layer, the second layer coupled to the first layer by hybrid bond interconnects having a first bond pad and a second bond pad, wherein: the first bond pad is coupled to a first via in the second die and the first bond pad is offset from the first via by a first dimension, and the second bond pad is coupled to a second via in the third die and the second bond pad is offset from the second via by a second dimension different than the first dimension.
  2. 2. The microelectronic assembly of claim 1, wherein the first bond pad is further offset from the first via in a first direction and the second bond pad is further offset from the second via in a second direction different than the first direction.
  3. 3. The microelectronic assembly of claim 1 or 2, wherein the first bond pad has a first thickness, and wherein the hybrid bond interconnects further include a third bond pad having a second thickness different than the first thickness.
  4. 4. The microelectronic assembly of any one of claims 1-3, wherein the hybrid bond interconnects further include a third bond pad, and the microelectronic assembly further comprising: a third via in the first die coupled to the third bond pad, wherein the third via is offset from the third bond pad by a third dimension different than the first dimension and the second dimension.
  5. 5. The microelectronic assembly of any one of claims 1-4, further comprising: a material around the second die and the third die in the second layer, the material including an inorganic dielectric.
  6. 6. The microelectronic assembly of claim 5, further comprising: a liner on and around the second die and the third die in the second layer between the material and the second die and the third die.
  7. 7. The microelectronic assembly of claim 6, wherein the liner has a thickness between 10 nanometers and 2 microns.
  8. 8. The microelectronic assembly of any one of claims 1-7, wherein the first via is at least partially within a cavity.
  9. 9. The microelectronic assembly of any one of claims 1-8, further comprising: an alignment mark.
  10. 10. The microelectronic assembly of any one of claims 1-9, further comprising: a substrate coupled to the first die in the first layer.
  11. 11. The microelectronic assembly of any one of claims 1-9, further comprising: an interposer coupled to the first die in the first layer; and a substrate coupled to the interposer.
  12. 12. A microelectronic assembly, comprising: a first die in a first layer; and a second die and a third die in a second layer, the second layer coupled to the first layer by interconnects including a first bond pad and a second bond pad in a dielectric material, wherein: the first bond pad is coupled to a first via in the second die and the first bond pad is offset from the first via in a first direction, and the second bond pad is coupled to a second via in the third die and the second bond pad is offset from the second via in a second direction different than the first direction.
  13. 13. The microelectronic assembly of claim 12, wherein the first bond pad is further offset from the first via by a first dimension and the second bond pad is further offset from the second via by a second dimension different than the first dimension.
  14. 14. The microelectronic assembly of claim 12 or 13, wherein the first bond pad has a first thickness, and wherein the interconnects further include a third bond pad having a second thickness different than the first thickness.
  15. 15. The microelectronic assembly of any one of claims 12-14, further comprising: a material around the second die and the third die in the second layer, the material including an inorganic dielectric.
  16. 16. The microelectronic assembly of claim 15, further comprising: a liner on and around the second die and the third die in the second layer between the material and the second die and the third die, the liner including silicon and nitrogen, or silicon, carbon, and nitrogen.
  17. 17. The microelectronic assembly of claim 16, wherein the liner has a thickness between 10 nanometers and 2 microns.
  18. 18. The microelectronic assembly of any one of claims 12-17, further comprising: a substrate coupled to the first die in the first layer.
  19. 19. The microelectronic assembly of any one of claims 12-17, further comprising: an interposer coupled to the first die in the first layer; and a substrate coupled to the interposer.
  20. 20. A microelectronic assembly, comprising: a first die in a first layer; and a second die and a third die in a second layer, wherein the second layer is coupled to the first layer by first interconnects having a first thickness and by second interconnects having a second thickness different than the first thickness, wherein the first interconnects and the second interconnects have a pitch between 50 nanometers and 10 microns.

Description

PACKAGING ARCHITECTURE FOR WAFER-SCALE KNOWN-GOOD-DIE HYBRID BONDING CROSS-REFERENCE TO RELATED APPLICATION [0001] This application claims the benefit of and priority to U.S. Non-Provisional Patent Application No. 18/345,437, filed 30 June 2023, entitled "PACKAGING ARCHITECTURE FOR WAFERSCALE KNOWN-GOOD-DIE HYBRID BONDING," the disclosure of which is hereby incorporated by reference in its entirety. TECHNICAL FIELD [0002] The present disclosure relates to techniques, methods, and apparatus directed to packaging architecture for wafer-scale known-good-die (KGD) hybrid bonding. BACKGROUND [0003] Electronic circuits, when commonly fabricated on a wafer of semiconductor material, such as silicon, are called integrated circuits (ICs). The wafer with such ICs is typically cut into numerous individual dies. The dies may be packaged into an IC package containing one or more dies along with other electronic components such as resistors, capacitors, and inductors. The IC package may be integrated onto an electronic system, such as a consumer electronic system, or servers, such as mainframes. BRIEF DESCRIPTION OF THE DRAWINGS [0004] Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings. [0005] FIG. 1A is a schematic cross-sectional view of an example microelectronic assembly according to some embodiments of the present disclosure. [0006] FIG. IB is a schematic cross-sectional view of a portion of the example microelectronic assembly of FIG. 1A. [0007] FIG. IC is a schematic cross-sectional view of another example microelectronic assembly according to some embodiments of the present disclosure. [0008] FIG. ID is a schematic cross-sectional view of yet another example microelectronic assembly according to some embodiments of the present disclosure. [0009] FIG. 2 is a schematic cross-sectional view of another example microelectronic assembly according to some embodiments of the present disclosure. [0010] FIG. 3 is a schematic cross-sectional view of yet another example microelectronic assembly according to some embodiments of the present disclosure. [0011] FIGS. 4A-4H are schematic cross-sectional views of various stages of manufacture of an example microelectronic assembly according to some embodiments of the present disclosure. [0012] FIGS. 5A-5C are schematic cross-sectional views of various stages of manufacture of another example microelectronic assembly according to some embodiments of the present disclosure. [0013] FIG. 6 is a cross-sectional view of a device package that includes one or more microelectronic assemblies in accordance with any of the embodiments disclosed herein. [0014] FIG. 7 is a cross-sectional side view of a device assembly that includes one or more microelectronic assemblies in accordance with any of the embodiments disclosed herein. [0015] FIG. 8 is a block diagram of an example computing device that includes one or more microelectronic assemblies in accordance with any of the embodiments disclosed herein. DETAILED DESCRIPTION Overview [0016] For purposes of illustrating IC packages described herein, it is important to understand phenomena that may come into play during assembly and packaging of ICs. The following foundational information may be viewed as a basis from which the present disclosure may be properly explained. Such information is offered for purposes of explanation only and, accordingly, should not be construed in any way to limit the broad scope of the present disclosure and its potential applications. [0017] Advances in semiconductor processing and logic design have permitted an increase in the amount of logic circuits that may be included in processors and other IC devices. As a result, many processors now have multiple cores that are monolithically integrated on a single die. Generally, these types of monolithic ICs are also described as planar since they take the form of a flat surface and are typically built on a single silicon wafer made from a monocrystalline silicon boule. The typical manufacturing process for such monolithic ICs is called a planar process, allowing photolithography, etching, heat diffusion, oxidation, and other such processes to occur on the surface of the wafer, such that active circuit elements (e.g., transistors and diodes) are formed on the planar surface of the silicon wafer. [0018] Current technologies permit hundreds and thousands of such active circuit elements to be formed on a single die so that numerous logic circuits may be enabled thereon. In such monolithic dies, the manufacturing process must be optimized for all the circuits equally, resulting in trade-offs between different circuits. In addition, because of the limitation of having to place circuits on a pl