EP-4736224-A1 - METHODS AND STRUCTURES FOR LOW TEMPERATURE HYBRID BONDING

Abstract

A semiconductor element is provided with a micro-structured metal layer over conductive features of a hybrid bonding surface. The micro-structured metal layer comprises fine metal grain microstructure, such as nanograins. The micro-structured metal layer can be formed over the conductive features by providing a metal oxide and reducing the metal oxide to metal. The micro-structured metal layer can be formed selectively if the metal oxide is formed by oxidation. When directly bonded to another element, the micro-structured metal layer forming strong bonds at the bonding interface can substantially reduce annealing temperature.

Inventors

• UZOH, CYPRIAN, EMEKA
• ZHAO, OLIVER
• GUEVARA, Gabriel, Z.
• SUWITO, DOMINIK
• KATKAR, RAJESH

Assignees

• Adeia Semiconductor Bonding Technologies Inc.

Dates

Publication Date

20260506

Application Date

20240624

Claims (20)

1. 1. A process for preparing a first element for hybrid bonding, the process comprising: providing a metal oxide layer over a conductive feature, wherein the conductive feature is at least partially embedded in a dielectric material, the conductive feature and the dielectric material forming a bonding layer of the first element; chemically reducing the metal oxide layer to form a metal layer; and preparing a bonding surface of the bonding layer of the first element for hybrid bonding to a second element.
2. 2. The process of Claim 1, wherein the metal oxide layer comprises metal oxide grains.
3. 3. The process of Claim 1, wherein the metal oxide layer comprises an oxide of a metal of the conductive feature.
4. 4. The process of Claim 1, wherein the metal layer comprises a layer of a metal of the conductive feature.
5. 5. The process of Claim 1 , wherein the metal layer is more conductive than the metal oxide layer.
6. 6. The process of Claim 1, wherein a metal of the conductive feature and a metal in the metal oxide layer comprise at least one of copper, nickel, gold, indium, molybdenum, cobalt, zinc, tungsten, tantalum, titanium, aluminum, copper, nickel, chromium, gold, indium, tin, platinum, silver, ruthenium, molybdenum, palladium, cobalt, zinc, tungsten, tantalum, titanium, or aluminum.
7. 7. The process of Claim 1, wherein the metal layer comprises nanograins.
8. 8. The process of Claim 7, wherein the nanograins have an average dimension in the range of about 2 nm to 100 nm.
9. 9. The process of Claim 8, wherein the nanograins have an average dimension in the range of about 8 nm to 80 nm.
10. 10. The process of Claim 8, wherein the nanograins have an average dimension in the range of about 5 nm to 60 nm.
11. 11. The process of Claim 1 , further comprising, before providing the metal oxide layer over the conductive feature, forming a recess in the conductive feature relative to an upper surface of the bonding layer.
12. 12. The process of Claim 11, wherein a depth of the recess is in the range of about 1 nm to 100 nm relative to the upper surface.
13. 13. The process of Claim 1, wherein providing the metal oxide layer over the conductive feature comprises oxidizing a conductive material disposed over the dielectric material and oxidizing a part of the conductive feature.
14. 14. The process of Claim 1, wherein providing the metal oxide layer over the conductive feature comprises oxidizing a layer of the conductive feature.
15. 15. The process of Claim 13 or 14, wherein the oxidizing comprises plasma oxidation.
16. 16. The process of Claim 13 or 14, wherein the oxidizing comprises thermal oxidation.
17. 17. The process of Claim 13 or 14, wherein the oxidizing comprises wet oxidation.
18. 18. The process of Claim 1, wherein providing the metal oxide layer over the conductive feature comprises sputtering the metal oxide layer onto the conductive feature.
19. 19. The process of Claim 1, wherein providing the metal oxide layer over the conductive feature comprises spin-coating the metal oxide layer onto the conductive feature.
20. 20. The process of Claim 1, wherein providing the metal oxide layer over the conductive feature comprises electrolytic or electroless deposition.

Description

METHODS AND STRUCTURES FOR LOW TEMPERATURE HYBRID BONDING BACKGROUND Field [0001] The field relates to direct bonding of microelectronics, and more particularly to hybrid bonding. Description of the Related Art [0002] The microelectronics industry has experienced tremendous growth over the past decades. However, the thirst of the market for ever higher input/output (I/O) density and faster connection between chips has been unquenchable. This demand has driven integrated circuit (IC) system designs into 3D architectures. Solder bumps and micro-bumps can provide vertical interconnects between chips by using small metal bumps on dies as one form of waferlevel packaging. Hybrid bonding can provide a solution for superior density of interconnect features. [0003] Hybrid bonding, such as the DBI® technology commercially available from Adeia of San Jose, CA, avoids the use of metal bumps, and instead connects dies in packages using direct mctal-to-mctal (c.g., coppcr-to-coppcr) conductive feature connections. In the bonding layer of each bonding element conductive features, such as metal contact pads, are embedded in a dielectric material. The hybrid bonding surface can be planarized by chemical mechanical polishing (CMP) and cleaned to remove particles and contaminants. Plasma activation can create active sites on the dielectric of the hybrid bonding surface of at least one of the two elements to be bonded. The two bonding elements are aligned precisely as they are brought together in a bonding equipment and the active sites on the bonding surfaces bond to each other. The dielectric bonding can be processed at room temperature. An annealing process can aid in bonding aligned conductive features, and can also strengthen bonds between the dielectric materials. [0004] While hybrid bonding has greatly improved the ability to form high density and reliable connections between microelectronics, there remains a need to improve yield, reduce cost and/or reduce thermal budget consumption. BRIEF DESCRIPTION OF THE DRAWINGS [0005] Specific implementations will now be described with reference to the following drawings, which are provided by way of example, and not limitation. [0006] FIGS. 1 - 5 are schematic cross-sectional views illustrating an example process for fabricating a semiconductor element having metal grains on conductive features for hybrid bonding. [0007] FIG. 6A is an SEM image of an upper surface of a copper contact pad. [0008] FIG. 6B is an SEM image of an upper surface of a copper contact pad after an oxidation and reducing process. [0009] FIGS. 7 - 9 are schematic cross-sectional views illustrating another example process for fabricating a semiconductor element having metal grains on conductive features for hybrid bonding. [0010] FIGS. 10 - 12 are schematic cross-sectional views illustrating an example process for hybrid bonding an element having metal grains on conductive features with another element. [0011] FIG. 13 is a schematic cross-sectional view of another example of a bonded structure, similar to that of FIG. 12. [0012] FIGS. 14 - 15 are schematic cross-sectional views illustrating an example process of hybrid bonding a wafer having metal grains on conductive features to another wafer. [0013] FIG. 16 is a schematic cross-sectional view of the bonded structure of FIG. 15 after singulation. [0014] FIGS. 17 - 21 are schematic cross-sectional views illustrating an example process for hybrid bonding a wafer having metal grains on conductive features with a plurality of dies. [0015] FIG. 22 is a schematic cross-sectional view of two microelectronic elements configured to be hybrid bonded together. [0016] FIG. 23 is a schematic cross-sectional view of a bonded structure comprising the two microelectronic elements in FIG. 22. DETAILED DESCRIPTION [0017] Annealing temperatures and annealing durations for forming direct conductor-to-conductor (e.g., metal-to-metal) bonding is of great importance in the fabrication of directly bonded components. Lower annealing temperatures and/or shorter annealing durations are desirable, for example, for reduced consumption of thermal budget and reduced stressed due to CTE mismatch. Various bonding layer structures and methods for producing such bonded semiconductor elements can be implemented to achieve lower annealing temperatures to sufficiently fuse contact pads or other conductive features of the bonded semiconductor elements together. One way in which annealing temperatures can be lowered includes providing a microstructure for the material of the conductive features, which can achieve bonding with lower annealing temperature. Providing conductive materials with microstructures, such as nanograins, can be expensive, however, and can also introduce greater contaminants into the conductors. [0018] FIGS. 1 - 5 illustrate an example embodiment of a fabrication process for forming a microstructure for conductive features, such as contact pads. FIG. 1 shows a schematic