EP-4736225-A1 - EMBEDDED CHIPLETS WITH BACKSIDE POWER DELIVERY NETWORK

Abstract

An assembly may include a base element comprising a base substrate having a frontside with active circuitry and a backside opposite the frontside, a first bonding layer disposed on the frontside of the base substrate and including a signal pad to convey an electrical signal to the active circuitry. The assembly may further include a first functional element comprising a first semiconductor substrate having a frontside with active circuitry and a backside opposite the frontside, a second bonding layer disposed on the frontside of the first semiconductor substrate, and a back surface of the first functional element having a first contact feature to connect to power or ground, wherein the first bonding layer is hybrid bonded to the second bonding layer.

Inventors

• CHANG, Xu
• KATKAR, RAJESH

Assignees

• Adeia Semiconductor Bonding Technologies Inc.

Dates

Publication Date

20260506

Application Date

20240624

Claims (20)

1. 1. An electronic assembly comprising: a base element comprising a base substrate having a frontside with active circuitry and a backside opposite the frontside, a first bonding layer disposed on the frontside of the base substrate and including a signal pad to convey an electrical signal to the active circuitry on the frontside of the base substrate; and a first functional element comprising a first semiconductor substrate having a frontside with active circuitry and a backside opposite the frontside, a second bonding layer disposed on the frontside of the first semiconductor substrate, and a back surface of the first functional element having a first contact feature to connect to power or ground, wherein the first bonding layer is hybrid bonded to the second bonding layer.
2. 2. The electronic assembly of Claim 1, further comprising an insulating material disposed along a side surface of the first functional element and on the first bonding layer.
3. 3. The electronic assembly of Claim 2, wherein the insulating material comprises an inorganic dielectric.
4. 4. The electronic assembly of Claim 3, wherein the insulating material comprises silicon oxide.
5. 5. The electronic assembly of Claim 2, wherein the insulating material comprises an organic dielectric.
6. 6. The electronic assembly of Claim 2, wherein the insulating material is formed from low temperature tetraethyl orthosilicate.
7. 7. The electronic assembly of Claim 1, further comprising an interconnect structure disposed on the back surface of the first functional element and electrically connected to the first contact feature.
8. 8. The electronic assembly of Claim 7, wherein the interconnect structure comprises a redistribution layer.
9. 9. The electronic assembly of Claim 7, wherein the interconnect structure comprises one or more metallization layers.
10. 10. The electronic assembly of Claim 7, wherein the interconnect structure comprises an intermediate interconnect layer and a global interconnect layer, wherein the intermediate interconnect layer is disposed near a back surface of the interconnect structure, wherein the global interconnect layer is disposed on the intermediate interconnect layer nearer to a front surface of the interconnect structure than the intermediate interconnect layer, and wherein the intermediate interconnect layer is in electrical communication with the global interconnect layer.
11. 11. The electronic assembly of Claim 10, wherein the interconnect structure further comprises an input/output (IO) pad disposed near the front surface of the interconnect structure, wherein the IO pad is in electrical communication with the global interconnect layer, and wherein the IO pad is exposed at the front surface of the interconnect structure.
12. 12. The electronic assembly of Claim 1, further comprising a second functional element comprising a second semiconductor substrate having a frontside with active circuitry and a backside opposite the frontside.
13. 13. The electronic assembly of Claim 12, wherein the second functional element comprises a third bonding layer disposed on the frontside of the second semiconductor substrate, wherein the third bonding layer is hybrid bonded to the first bonding layer.
14. 14. The electronic assembly of Claim 12, wherein the backside of the second functional element is hybrid bonded to the first bonding layer, and wherein the second functional element comprises a second contact feature disposed on a front surface of the second functional element.
15. 15. An electronic assembly comprising: a base element comprising a base substrate having a frontside and a backside opposite the frontside, a first bonding layer disposed on the frontside of the base substrate; a first functional element comprising a first semiconductor substrate having a frontside with active circuitry and a backside opposite the frontside, a second bonding layer disposed on the frontside of the first semiconductor substrate, and a back surface of the first functional element comprising a first contact feature to connect to power or ground; and a second functional element comprising a second semiconductor substrate having a frontside with active circuitry and a backside opposite the frontside, wherein the first bonding layer is hybrid bonded to the second bonding layer and the second semiconductor element is hybrid bonded to the base element.
16. 16. The electronic assembly of Claim 15, wherein the backside of the second semiconductor substrate is hybrid bonded to the base element, and wherein the second functional element comprises a second contact feature disposed on a front surface of the second functional element to connect to power or ground.
17. 17. The electronic assembly of Claim 15, wherein the frontside of the second functional element is hybrid bonded to a front surface of the base substrate, and wherein a back surface of the second functional element comprises a second contact feature to connect to power or ground.
18. 18. The electronic assembly of Claim 15, wherein the first bonding layer comprises a contact feature to convey an electrical signal to the active circuitry on the frontside of the base substrate.
19. 19. The electronic assembly of Claim 15, further comprising an insulating material disposed along a side surface of the first functional element and on the first bonding layer.
20. 20. The electronic assembly of Claim 19, wherein the insulating material comprises an inorganic dielectric.

Description

EMBEDDED CHIPLETS WITH BACKSIDE POWER DELIVERY NETWORK CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application claims priority to U.S. Application No. 18/401082, filed December 29, 2023, titled “EMBEDDED CHIPLETS WITH BACKSIDE POWER DELIVERY NETWORK,” U.S. Application No. 18/401124, filed December 29, 2023, titled, “EMBEDDED CHIPLETS WITH BACKSIDE POWER DELIVERY NETWORK,” and U.S. Provisional Application No. 63/511555, filed June 30, 2023, titled “EMBEDDED CHIPLETS WITH BACKSIDE POWER DELIVERY NETWORK,” the disclosures of which are incorporated herein by reference in their entirety for all purposes. BACKGROUND Technical Field [0002] This disclosure relates to semiconductor device structures and methods. In particular, some embodiments are directed to methods and structures for providing backside power delivery to embedded chiplets. Description of Related Art [0003] The approaches described in this section are approaches that could be pursued, but not necessarily approaches that have been previously conceived or pursued. Therefore, unless otherwise indicated, it should not be assumed that any of the approaches described in this section qualify as prior art merely by virtue of their inclusion in this section. [0004] As features in semiconductor devices continue to shrink, power delivery issues are of increasing concern. Electrical isolation issues, limitations on feature sizes due to the high density of circuit elements and interconnects, losses due to traversing large numbers of metal layers, and so forth can make it difficult to efficiently provide power to semiconductor devices. Tight spacing between interconnects can cause interference between power and signaling. Accordingly, there is a need for improved semiconductor device assemblies. SUMMARY [0005] The systems, methods, and devices described herein each have several aspects, no single one of which is solely responsible for its desirable attributes. Without limiting the scope of this disclosure, several non-limiting features will now be described briefly. [0006] In some embodiments, the techniques described herein relate to an electronic assembly including: a base element including a base substrate having a frontside with active circuitry and a backside opposite the frontside, a first bonding layer disposed on the frontside of the base substrate and including a signal pad to convey an electrical signal to the active circuitry on the frontside of the base substrate; and a first functional element including a first semiconductor substrate having a frontside with active circuitry and a backside opposite the frontside, a second bonding layer disposed on the frontside of the first semiconductor substrate, and a back surface of the first functional element having a first contact feature to connect to power or ground, wherein the first bonding layer is hybrid bonded to the second bonding layer. [0007] In some aspects, the techniques described herein relate to an electronic assembly, further including an insulating material disposed along a side surface of the first functional element and on the first bonding layer. [0008] In some aspects, the techniques described herein relate to an electronic assembly, wherein the insulating material includes an inorganic dielectric. [0009] In some aspects, the techniques described herein relate to an electronic assembly, wherein the insulating material includes silicon oxide. [0010] In some aspects, the techniques described herein relate to an electronic assembly, wherein the insulating material includes an organic dielectric. [0011] In some aspects, the techniques described herein relate to an electronic assembly, wherein the insulating material is formed from low temperature tetraethyl orthosilicate. [0012] In some aspects, the techniques described herein relate to an electronic assembly, further including an interconnect structure disposed on the back surface of the first functional element and electrically connected to the first contact feature. [0013] In some aspects, the techniques described herein relate to an electronic assembly, wherein the interconnect structure includes a redistribution layer. [0014] In some aspects, the techniques described herein relate to an electronic assembly, wherein the interconnect structure includes one or more metallization layers. [0015] In some aspects, the techniques described herein relate to an electronic assembly, wherein the interconnect structure includes an intermediate interconnect layer and a global interconnect layer, wherein the intermediate interconnect layer is disposed near a back surface of the interconnect structure, wherein the global interconnect layer is disposed on the intermediate interconnect layer nearer to a front surface of the interconnect structure than the intermediate interconnect layer, and wherein the intermediate interconnect layer is in electrical communication with the global interconnect layer. [0016] In some aspects, the techniques desc