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EP-4736228-A1 - SEMICONDUCTOR PACKAGE WITH DIRECTIONAL LOCKING STRUCTURE

EP4736228A1EP 4736228 A1EP4736228 A1EP 4736228A1EP-4736228-A1

Abstract

The present disclosure relates to a semiconductor package. The semiconductor package includes a semiconductor die, molding material, and a conductive structure. The conductive structure is at least partly stacked with the semiconductor die, and the conductive structure includes a plurality of slots positioned around a point of the semiconductor die. The plurality of slots is configured to equalize thermal stresses during the operation of the semiconductor die about the point of the semiconductor die, where the thermal stresses are associated with coefficient of thermal expansion mismatches between the conductive structure and the molding material. In addition, at least a portion of the molding material is in contact with the conductive structure.

Inventors

  • CHI, WILLIAM THOMAS
  • RAHEJA, UTKARSH
  • GANDIKOTA, Sesha Sai Srikant Sarma
  • EMBLETON, STEVEN THOMAS

Assignees

  • Tesla, Inc.

Dates

Publication Date
20260506
Application Date
20240624

Claims (20)

  1. 1. A semiconductor package comprising: a semiconductor die comprising a field effect transistor; molding material; and a conductive structure at least partly stacked with the semiconductor die, the conductive structure comprising a plurality of slots positioned around a point of the semiconductor die, the plurality of slots configured to equalize thermal stresses during operation of the semiconductor die about the point of the semiconductor die, the thermal stresses being associated with coefficient of thermal expansion mismatches between the conductive structure and the molding material, and at least a portion of the molding material being in contact with the conductive structure.
  2. 2. The semiconductor package of claim 1, wherein the plurality of slots are oriented in a radial pattern about the point of the semiconductor die.
  3. 3. The semiconductor package of claim 1, wherein each slot of the plurality of slots has length in a direction extending away from the point and a width in a direction perpendicular to the length, the length being long than the width.
  4. 4. The semiconductor package of claim 1, further comprising a heat spreader on an opposite side of the semiconductor die than the conductive structure, wherein each slot of the plurality of slots is positioned at least partly over the heat spreader.
  5. 5. The semiconductor package of claim 1, wherein each slot of the plurality of slots is positioned at least partly over the semiconductor die.
  6. 6. The semiconductor package of claim 1, wherein the conductive structure is a lead frame.
  7. 7. The semiconductor package of claim 6, wherein the lead frame comprises a plurality of leads along a side of the semiconductor package, the plurality of leads comprising two source leads, a sensing lead positioned between the two source leads, and a gate lead positioned between the two source leads.
  8. 8. The semiconductor package of claim 6, further comprising a die clip positioned between the semiconductor die and a portion of the lead frame, wherein the die clip and the lead frame are joined at connection points.
  9. 9. The semiconductor package of claim 1, wherein the conductive structure is a die paddle.
  10. 10. A semiconductor package comprising: a semiconductor die; molding material; and a lead frame at least partly stacked with the semiconductor die and comprising a plurality of slots positioned around a point of the semiconductor die, the plurality of slots configured to equalize thermal stresses about the point of the semiconductor die, and at least a portion of the molding material being in contact with the lead frame.
  11. 11. The semiconductor package of claim 10, wherein the plurality of slots are oriented in a radial pattern about the point of the semiconductor die.
  12. 12. The semiconductor package of claim 10, wherein at least one slot of the plurality of slots has a rectangular shape.
  13. 13. The semiconductor package of claim 10, wherein each slot of the plurality of slots has length in a direction extending away from the point and a width in a direction perpendicular to the length, the length being long than the width.
  14. 14. The semiconductor package of claim 10, wherein the point is a center point of the semiconductor package.
  15. 15. The semiconductor package of claim 10, further comprising a heat spreader on an opposite side of the semiconductor die than the lead frame, wherein each slot of the plurality of slots is positioned at least partly over the heat spreader.
  16. 16. The semiconductor package of claim 10, wherein two or more slots of the plurality of slots have different lengths.
  17. 17. The semiconductor package of claim 10, wherein the semiconductor die comprises a field effect transistor, and wherein the lead frame comprises a plurality of leads comprising two source leads electrically connected to a source of the field effect transistor, a gate lead electrically connected to a gate of the field effect transistor, and a sensing lead, and wherein the plurality of leads is positioned on a first side of the lead frame, and wherein the gate lead and the sensing lead are positioned between the two source leads.
  18. 18. The semiconductor package of claim 10, wherein the thermal stresses are caused by coefficient of thermal expansion (CTE) mismatches between the lead frame and the molding material.
  19. 19. The semiconductor package of claim 10, further comprising a thermistor electrically connected to a sensing lead of the lead frame.
  20. 20. The semiconductor package of claim 10, further comprising a die coating material positioned between the die and the lead frame, the slots dimensioned to allow the die coating material to be injected therethrough during manufacture.

Description

TSLA.789WO PATENT SEMICONDUCTOR PACKAGE WITH DIRECTIONAL LOCKING STRUCTURE CROSS-REFERENCE TO RELATED APPLICATION [0001] This application claims the benefit of U.S. Provisional Patent Application No. 63/510,569, entitled “IMPROVED SEMICONDUCTOR DEVICE PACKAGES,” filed on June 27, 2023, the disclosure of which is hereby incorporated by reference in its entirety and for all purposes. BACKGROUND Technical Field [0002] This application relates to semiconductor device packages. In particular, some embodiments relate to semiconductor packages with a dual-sided heat dissipation structure and related manufacturing methods. Some embodiments relate to semiconductor packages with directional locking structures, having one or more slots on a lead frame of the semiconductor packages. Some embodiments relate to semiconductor packages with nested pinout structures, having drain leads on one side and device leads (such as gate lead and/or sensing lead) on another side. Description of Related Technology [0003] Semiconductor devices are used in a wide variety of applications. In some applications, semiconductor devices can experience high electrical loads that can result in significant heating of the semiconductor device. There may be technical problems associated with high electrical loads, such as detrimental heating of the semiconductor device from the high load. In some applications, semiconductor devices can experience failure of interface connections between components of the semiconductor devices due to uneven thermal stress, such as uneven thermal expansion or contraction across the components of the semiconductor devices. There may be technical problems associated with interface connection failure during the operations of the semiconductor devices. In some applications, semiconductor devices can experience. SUMMARY [0004] The innovations described in the claims each have several aspects, no single one of which is solely responsible for its desirable attributes. Without limiting the scope of the claims, some prominent features of this disclosure will now be briefly described. [0005] One aspect of the present disclosure is a semiconductor package with a dual sided heat dissipation structure. The semiconductor package includes a semiconductor die having a first side and a second side, a heat spreader on the first side of the semiconductor die, a lead frame on the second side of the semiconductor die, and a die clip positioned between the semiconductor die and a portion of the lead frame. The second side is positioned opposite to the first side. The die clip is positioned between the semiconductor die and a portion of the lead frame. In addition, the die clip and the lead frame are joined at connection points. [0006] In one embodiment, the die clip can include openings at the connection points. [0007] In one embodiment, the lead frame can include a gate lead and a Kelvin source lead. A first connection point of the connection points can join the die clip and the gate lead, and a second connection point of the connection points can join the die clip and the Kelvin source lead. [0008] In one embodiment, the semiconductor package can be free from solder between the lead frame and the die clip. [0009] In one embodiment, the connection points can provide alignment points between the lead frame and the die clip for welding the die clip and the lead frame. [0010] In one embodiment, the semiconductor die can include a field effect transistor. Additionally, the lead frame can include electrical contact points to terminals of the semiconductor die, and the terminals of the semiconductor die can include a source terminal, a gate terminal, and a Kelvin source terminal. [0011] In one embodiment, a first side of the lead frame can include a plurality of leads. The plurality of leads can include two source leads connected to the source terminal of the semiconductor die, a gate lead connected to the gate terminal of the semiconductor die, and a Kelvin source lead connected to the Kelvin source terminal of the semiconductor die. The gate lead and the Kelvin source lead can be positioned between the two gate leads. In addition, a second side of the lead frame is positioned opposite to the first side of the lead frame. The lead frame can further include one or more drain leads electrically connected to the drain terminal of the semiconductor die. Furthermore, the semiconductor package can include a sensing lead on the first side of the lead frame, and the sensing lead can be positioned between the two source leads. [0012] In one embodiment, the lead frame can include a lead, and at least a portion of the lead can be extended beyond the heat spreader can be flat. [0013] In one embodiment, the semiconductor package can further include a thermistor die. In addition, the lead frame can include a thermistor lead electrically connected to a terminal of the thermistor die. [0014] In one embodiment, the semiconductor package can further incl