EP-4736229-A1 - HEAVILY DOPED SEMICONDUCTOR DEVICES FOR POWER DISTRIBUTION

Abstract

A device including a first integrated device die and a semiconductor device. The first integrated device die can include a die insulating layer and a die conductive feature at least partially embedded in the die insulating layer. The semiconductor device can include a first insulating layer on the first surface, a device conductive feature at least partially embedded in the first insulating layer, and a first heavily doped semiconductor material electrically connected to the device conductive feature. The die conductive feature can be connected to power or ground through at least the first heavily doped semiconductor material.

Inventors

• KATKAR, RAJESH
• UZOH, CYPRIAN, EMEKA
• HABA, BELGACEM

Assignees

• Adeia Semiconductor Bonding Technologies Inc.

Dates

Publication Date

20260506

Application Date

20240626

Claims (20)

1. 1. A semiconductor device, comprising: a first layer comprising a first heavily doped semiconductor material and a first insulating bonding layer; a second layer comprising a second heavily doped semiconductor material and a second insulating bonding layer; and a first via extending through the second layer and electrically connecting to the first heavily doped semiconductor material, wherein the first layer and the second layer are directly bonded to one another without an intervening adhesive.
2. 2. The semiconductor device of Claim 1, wherein the first via connects one of power or ground to the first heavily doped semiconductor material of the first layer.
3. 3. The semiconductor device of Claim 1, wherein the first layer further comprises first conductive features and the second layer further comprises second conductive features, wherein the first conductive features and the second conductive features are directly bonded to one another without an intervening adhesive.
4. 4. The semiconductor device of Claim 3, wherein the second layer is hybrid bonded to the first layer such that the second insulating bonding layer of the second layer is directly bonded to the first insulating bonding layer of the first layer, and the second conductive features of the second layer are directly bonded to the first conductive features of the first layer.
5. 5. The semiconductor device of Claim 1, further comprising a third layer comprising a third heavily doped semiconductor material and a third insulating bonding layer, wherein the second layer and the third layer are directly bonded to one another without an intervening adhesive.
6. 6. The semiconductor device of Claim 1, further comprising insulating rings around the first via of the first layer.
7. 7. The semiconductor device of Claim 1, wherein the first heavily doped semiconductor material is embedded with dielectric spacers, the dielectric spacers separating the first heavily doped semiconductor material into heavily doped semiconductor islands.
8. 8. The semiconductor device of Claim 7, wherein a first heavily doped semiconductor island of the heavily doped semiconductor islands is connected to a first power source at a first voltage and a second heavily doped semiconductor island of the heavily doped semiconductor islands is connected to ground.
9. 9. The semiconductor device of Claim 7, wherein the heavily doped semiconductor islands are configured to connect to different electrical potentials.
10. 10. The semiconductor device of Claim 1, wherein the second heavily doped semiconductor material is connected to electrical ground.
11. 11. The semiconductor device of Claim 1, wherein the first heavily doped semiconductor material includes an insulating end cap.
12. 12. The semiconductor device of Claim 1, wherein each of the first and second heavily doped semiconductor materials has a dopant concentration of at least 10 18 atoms/cm 3 and less than 10 22 atoms/cm 3 .
13. 13. The semiconductor device of Claim 1, further comprising: a fluid inlet; an inlet channel connected to the fluid inlet; a fluid outlet; an outlet channel connected to the outlet; and one or more cooling channels extending through at least the first insulating layer, wherein the one or more cooling channels connect to the inlet channel and the outlet channel.
14. 14. The semiconductor device of Claim 13, wherein the inlet, the inlet channel, and the one or more cooling channels are arranged to allow a fluid to flow into the semiconductor device such that the inlet channel and the one or more cooling channels integrally connect such that the fluid can flow from the inlet channel to the one or more cooling channels.
15. 15. The semiconductor device of Claim 13, wherein the outlet, the outlet channel, and the one or more cooling channels are arranged to allow a fluid to flow from the semiconductor device such that the one or more cooling channels and the outlet channel integrally connect such that the fluid can flow from the one or more cooling channels to the outlet channel to exit the semiconductor device at the outlet.
16. 16. The semiconductor device of Claim 13, wherein the inlet, the inlet channel, the outlet, the outlet channel, and the one or more cooling channels include a cavity, wherein the cavity encloses a cooling fluid.
17. 17. The semiconductor device of Claim 16, wherein the cooling fluid is a dielectric fluid.
18. 18. The semiconductor device of Claim 13, wherein the inlet, the inlet channel, the outlet, the outlet channel, and the one or more cooling channels include a cavity and a barrier surrounding the cavity, wherein the barrier separates the cavity from the first insulating bonding layer.
19. 19. A bonded structure including the semiconductor device of Claim 1, the bonded structure further comprising an integrated device die, the integrated device die comprising a front surface and a back surface, wherein the semiconductor device is directly bonded to the integrated device die.
20. 20. A bonded structure comprising: a first integrated device die comprising a front surface and a back surface, the first integrated device die including a die insulating layer and a die conductive feature at least partially embedded in the die insulating layer; and a semiconductor device having a first surface and a second surface opposite the first surface, the semiconductor device including a first insulating layer on the first surface, a device conductive feature at least partially embedded in the first insulating layer, and a first heavily doped semiconductor material electrically connected to the device conductive feature, the first insulating layer directly bonded to the die insulating layer without an intervening adhesive, and the die conductive feature directly bonded to the device conductive feature without an intervening adhesive, wherein the die conductive feature is connected to power or ground through at least the first heavily doped semiconductor material.

Description

HEAVILY DOPED SEMICONDUCTOR DEVICES FOR POWER DISTRIBUTION INCORPORATION BY REFERENCE [0001] This application claims priority to U.S. Non-Provisional Application No. 18/745238, filed June 17, 2024, and U.S. Provisional Application No. 63/511598, filed June 30, 2023, and which is incorporated herein by reference. Any and all applications for which a foreign or domestic priority claim is identified in the Application Data Sheet as filed with the present application are hereby incorporated by reference under 37 CFR 1.57. BACKGROUND Field [0002] The field relates to bonded structures, and, in particular, to bonded structures in which semiconductor materials are heavily doped for power distribution. Description of the Related Art [0003] As features in semiconductor devices continue to shrink, power delivery issues are of increasing concern, as thermal issues, electrical isolation issues, limitations on feature sizes, losses due to traversing large numbers of metal layers, and so forth make it difficult to efficiently provide power to semiconductor devices. Accordingly, there remains a continuing need for improved power delivery devices. BRIEF DESCRIPTION OF THE DRAWINGS [0004] The detailed description is set forth with reference to the accompanying figures. The use of the same numbers in different figures indicates similar or identical items. [0005] For this discussion, the devices and systems illustrated in the figures are shown as having a multiplicity of components. Various implementations of devices and/or systems, as described herein, may include fewer components and remain within the scope of the disclosure. Alternatively, other implementations of devices and/or systems may include additional components, or various combinations of the described components, and remain within the scope of the disclosure. [0006] FIG. 1A depicts a schematic side sectional view of power delivery device soldered to an integrated device die. [0007] FIG. IB depicts a schematic side sectional view of a power delivery device bonded with multiple integrated device dies and an interposer. [0008] FIGS. 2A-2B depict a schematic side sectional view of a bonded structure including a semiconductor device comprising an interposer configured to deliver power to one or more integrated device dies. [0009] FIGS. 3A-3D are schematic side section views of a semiconductor device with heavily doped semiconductor materials, according to various embodiments. [0010] FIG. 4 is a schematic side sectional view of a semiconductor device with heavily doped semiconductor materials connected to a back surface of an integrated device die. [0011] FIG. 5 is a schematic side sectional view of a semiconductor device with heavily doped semiconductor materials connected to a front surface of an integrated device die. [0012] FIG. 6 is schematic side sectional view of a semiconductor device with heavily doped semiconductor materials connected to multiple integrated device dies and serving as an interposer, with power delivery supplied from a top side of the semiconductor device. [0013] FIG. 7 is schematic side sectional view of a semiconductor device with heavily doped semiconductor materials connected to multiple integrated device dies and serving as an interposer, with power delivery supplied from a bottom side of the semiconductor device. [0014] FIG. 8A is a schematic side sectional view of a semiconductor device with heavily doped semiconductor materials and cooling channels mounted to (e.g., directly hybrid bonded to) a back surface of an integrated device die. [0015] FIG. 8B is a schematic top view of a semiconductor device with heavily doped semiconductor materials temperature controlled by cooling channels. [0016] FIG. 9A is a schematic side sectional view of semiconductor elements prepared for direct hybrid bonding without an intervening adhesive. [0017] FIG. 9B is a schematic side sectional view of a directly hybrid bonded structure without an intervening adhesive. DETAILED DESCRIPTION [0018] Power distribution or power delivery devices may provide power to electronic components (such as integrated device dies) through the use of metal planes or metal lines that have high coefficients of thermal expansion (CTE). Metal planes within power delivery devices are formed of a thickness to support the power requirements of one integrated device die or a stack of integrated device dies. Consequently, stacked dies lack adequate power supply from the power delivery devices because of the limited power capabilities of the metal planes. In addition, the metal planes add thermomechanical stresses to the overall stack due to CTE differential between the die or die stack and the metal planes. Additionally, devices typically are limited by space for vias to be connected to the metal plane. Accordingly, there remains a continued need for improved power distribution or delivery devices. [0019] Providing the correct amount of power to one or multiple integrated device di