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EP-4736231-A1 - HIGH-BANDWIDTH THREE-DIMENSIONAL (3D) DIE STACK

EP4736231A1EP 4736231 A1EP4736231 A1EP 4736231A1EP-4736231-A1

Abstract

Examples herein describe techniques for producing a three-dimensional (3D) die stack. The techniques include stacking a first die on top of a second die. The first die is offset from the second die in at least one of an x-direction and a y-direction, and a first routing sub-region of the first die aligns with a second routing sub-region of the second die. The techniques further include stacking a third die on top of the second die. The third die is offset from the second die in at least one of the x-direction and the y-direction, and a third routing sub-region of the third die aligns with a fourth routing sub-region of the second die.

Inventors

  • VOOGEL, MARTIN L.
  • KLEIN, MATTHEW H.

Assignees

  • Xilinx, Inc.

Dates

Publication Date
20260506
Application Date
20240617

Claims (15)

  1. 1 . A method of producing a three-dimensional (3D) die stack, comprising: stacking a first die on top of a second die, wherein the first die is offset from the second die in at least one of an x-direction and a y-direction, and a first routing sub-region of the first die aligns with a second routing sub-region of the second die; and stacking a third die on top of the second die, wherein the third die is offset from the second die in at least one of the x-direction and the y-direction, and a third routing sub-region of the third die aligns with a fourth routing sub-region of the second die.
  2. 2. The method of claim 1 , wherein the first routing sub-region of the first die communicates with the third routing sub-region of the third die via the second routing sub-region and the fourth routing sub-region.
  3. 3. The method of claims 1 or 2, wherein the first die does not directly communicate with the third die.
  4. 4. The method of any of claims 1-3, wherein the first die, the second die, and the third die comprise programmable logic (PL), and the first routing sub-region, the second routing sub-region, the third routing sub-region, and the fourth routing subregion comprise fabric sub-regions.
  5. 5. The method of any of claims 1-4, further comprising stacking a fourth die on top of the first die and the third die, wherein a fifth routing sub-region of the fourth die aligns with at least a portion of the second routing sub-region of the second die, and a sixth routing sub-region of the fourth die aligns with at least a portion of the fourth routing sub-region of the second die, and wherein the fifth routing sub-region of the fourth die communicates with the second routing sub-region via the first routing subregion of the first die, and the sixth routing sub-region of the fourth die communicates with the fourth routing sub-region via the third routing sub-region of the third die.
  6. 6. The method of any of claims 1-5, wherein the first die, the second die, and the third die comprise at least one of a central processing unit (CPU) die, a graphics processing unit (GPU) die, a programmable logic (PL) die, a system-on-chip (SoC) die, an application-specific integrated circuit (ASIC) die, and a memory die.
  7. 7. The method of any of claims 1 -6, wherein stacking the first die on top of the second die comprises hybrid oxide bonding a first wafer comprising the first die to a second wafer comprising the second die, and stacking the third die on top of the second die comprises hybrid oxide bonding a third wafer comprising the third die to the second wafer.
  8. 8. The method of any of claims 1-7, wherein the first die is included in a first wafer comprising a first plurality of dice, and the second die is included in a second wafer comprising a second plurality of dice, wherein each die included in the first plurality of dice is offset from each die included in the second plurality of dice in at least one of the x-direction and the y-direction, and at least one routing sub-region of each die included in the first plurality of dice aligns with at least one routing subregion of a die included in the second plurality of dice.
  9. 9. The method of any of claims 1-8, wherein a pitch of electrical connections between (i) a bottom of the first die and a top of the second die, and (ii) between a bottom of the third die and the top of the second die is less than 5 microns.
  10. 10. The method of any of claims 1-9, wherein the first routing sub-region comprises a first field-programmable gate array (FPGA) fabric, the second routing sub-region comprises a second FPGA fabric, the third routing sub-region comprises a third FPGA fabric, and the fourth routing sub-region comprises a fourth FPGA fabric.
  11. 11. A three-dimensional (3D) die stack, comprising: a first die stacked on top of a second die, wherein the first die is offset from the second die in at least one of an x-direction and a y-direction, and a first routing sub-region of the first die aligns with a second routing sub-region of the second die; and a third die stacked on top of the second die, wherein the third die is offset from the second die in at least one of the x-direction and the y-direction, and a third routing sub-region of the third die aligns with a fourth routing sub-region of the second die.
  12. 12. The 3D die stack of claim 11 , wherein the first routing sub-region of the first die communicates with the third routing sub-region of the third die via the second routing sub-region and the fourth routing sub-region.
  13. 13. The 3D die stack of claims 11 or 12, wherein the first die does not directly communicate with the third die.
  14. 14. The 3D die stack of any of claims 11 -13, wherein the first die, the second die, and the third die comprise at least one of a central processing unit (CPU) die, a graphics processing unit (GPU) die, a programmable logic (PL) die, a system-on- chip (SoC) die, an application-specific integrated circuit (ASIC) die, and a memory die.
  15. 15. The 3D die stack of any of claims 11 -14, wherein the first die is included in a first wafer comprising a first plurality of dice, and the second die is included in a second wafer comprising a second plurality of dice, wherein each die included in the first plurality of dice is offset from each die included in the second plurality of dice in at least one of the x-direction and the y-direction, and at least one routing sub-region of each die included in the first plurality of dice aligns with at least one routing subregion of a die included in the second plurality of dice.

Description

HIGH-BANDWIDTH THREE-DIMENSIONAL (3D) DIE STACK TECHNICAL FIELD [0001] Examples of the present disclosure generally relate to Integrated circuit (IC) devices, and more specifically, to a high-bandwidth 3D die stack. BACKGROUND [0002] Increasingly, high-performance computing applications are implementing Integrated circuit (IC) packaging techniques that enable multiple dice to communicate within a single package. In one such technique (commonly referred to as “2.5D" IC packaging), multiple dice are coupled to an interposer that includes several metal layers for routing signals between the dice. These techniques have been widely adopted by industry, but suffer from a number of drawbacks. SUMMARY [0003] Techniques for producing a three-dimensional (3D) die stack. The techniques include stacking a first die on top of a second die. The first die is offset from the second die in at least one of an x-direction and a y-direction, and a first routing sub-region of the first die aligns with a second routing sub-region of the second die. The techniques further include stacking a third die on top of the second die. The third die is offset from the second die in at least one of the x-direction and the y-direction, and a third routing sub-region of the third die aligns with a fourth routing sub-region of the second die. [0004] One example described herein is a 3D die stack. The 3D die stack includes a first die stacked on top of a second die. The first die is offset from the second die in at least one of an x-direction and a y-direction, and a first routing subregion of the first die aligns with a second routing sub-region of the second die. The 3D die stack further includes a third die stacked on top of the second die. The third die is offset from the second die in at least one of the x-direction and the y-direction, and a third routing sub-region of the third die aligns with a fourth routing sub-region of the second die. [0005] One example described herein is a computing system. The computing system includes a memory and a 3D die stack coupled to the memory. The 3D die stack includes a first die stacked on top of a second die. The first die is offset from the second die in at feast one of an x-direction and a y-direction, and a first routing sub-region of the first die aligns with a second routing sub-region of the second die. The 3D die stack further includes a third die stacked on top of the second die. The third die is offset from the second die in at feast one of the x-direction and the y- direction, and a third routing sub-region of the third die aiigns with a fourth routing sub-region of the second die. BRIEF DESCRIPTION OF DRAWINGS [0006] So that the manner in which the above recited features can be understood in detail, a more particular description, briefly summarized above, may be had by reference to example implementations, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical example implementations and are therefore not to be considered limiting of its scope. [0007] Fig. 1 is a block diagram of a SoC that includes a data processing engine array and programmable logic, according to an example. [0008] Fig. 2 is a block diagram of a data processing engine in the data processing engine array, according to an example. [0009] Fig. 3A illustrates a schematic cross-sectional view of a three-dimensional (3D) die stack including two PL die types, according to an example. [0010] Fig. 3B illustrates an exploded top-level view of the 3D die stack of Fig. 3A. [0011] Fig. 4 illustrates a schematic cross-sectional view of a 3D die stack including a single programmable logic (PL) die type, according to an example. [0012] Fig. 5 illustrates multiple logic sub-regions included in each PL die. [0013] Figs. 6A-6C illustrate schematic cross-sectional views of different 3D die stacks including a first type of PL dice and/or a second type of PL dice, according to several examples. [0014] Figs. 6D-6O illustrate schematic cross-sectional views of different 3D die stacks including various types of dice, according to several examples. [0015] Fig. 7 illustrates a technique for generating different types of heterogeneous dice by offsetting a single set of mask patterns, according to an example. [0016] Figs. 8 and 9 illustrate techniques for generating different types of heterogeneous dice by offsetting a single set of mask patterns and cutting the resulting die along the x-direction or the y-direction, according to several examples. [0017] Figs. 10A-10C illustrate a technique for generating large-scale 3D die stacks by offsetting a single set of mask patterns, according to an example. [0018] Fig. 11 is a flowchart of a method for producing a 3D die stack, according to an example. [0019] Fig. 12 is a flowchart of a method for producing a 3D die stack by stepping a set of mask patterns in an offset manner, according to an example. [0020] To facilitate un