EP-4736232-A1 - METHODS OF FORMING WAFER LEVEL MULTI-DIE SYSTEM FABRIC INTERCONNECT STRUCTURES

Abstract

Microelectronic integrated circuit package structures include a package substrate with a first die over the package substrate, and a second die adjacent to the first die, such that first sides of the first die and the second die are on a thermal solution. A bridge structure is directly on a portion of each of second sides of the first and second dies, such that the second sides include integrated circuit contact structures. Bridge via structures couple the integrated circuit contact structures to the bridge structure.

Inventors

• MALLIK, DEBENDRA
• VISWANATH, RAM
• BRUN, Xavier

Assignees

• INTEL Corporation

Dates

Publication Date

20260506

Application Date

20231211

Claims (20)

1. 1 . An apparatus, comprising: a first die comprising a first side and a second side; a second die adjacent the first die, the second die comprising a first side and a second side; a dielectric spacer in a space between the first die and the second die; a bridge structure interconnecting the first die and the second die, wherein the bridge structure spans the space between the first die and the second die, a first portion of the bridge structure is directly on a first metal feature of the first side of the first die, and a second portion of the bridge structure is directly on a second metal feature of the first side of the second die; and a package substrate, wherein the first side of the first die and the first side of the second die are coupled to a first side of the package substrate.
2. 2. The apparatus of claim 1, wherein a thermal solution is on the second sides of the first die and the second die.
3. 3. The apparatus of claim 2, wherein the thermal solution comprises a bulk silicon wafer.
4. 4. The apparatus as in any of the proceeding claims wherein the bridge structure comprises a plurality of conductive traces on an inorganic dielectric layer, wherein a first terminal end of an individual one of the plurality of conductive traces is coupled to the first metal feature and a second terminal end of the individual one of the plurality of conductive traces is coupled to the second metal feature.
5. 5. The apparatus of claim 2, wherein a first side of the dielectric spacer is directly on the thermal solution and an inorganic dielectric layer is between the bridge structure a second side of the dielectric spacer.
6. 6. The apparatus of claim 4, wherein a system level metal region is adjacent and noncontiguous with the bridge structure, wherein the system level metal region comprises a thickness that is substantially the same as a thickness of the bridge structure, and wherein the inorganic dielectric layer is between the system level metal region and a second die active area.
7. 7. The apparatus of claim 6, wherein the system level metal region comprises a plurality of conductive traces wherein each individual one of the plurality of conductive traces comprises one or more via structures, wherein the one or more via structures are in direct contact with a first die active area or the second die active area.
8. 8. The apparatus of claim 6, wherein one or more conductive bumps are on the system level metal region and are adjacent to the bridge structure.
9. 9. The apparatus of claim 8, wherein a dielectric layer is on the system level metal region, wherein the one or more conductive bumps are adjacent the dielectric layer.
10. 10. The apparatus as in any of the proceeding claims wherein the first side of the first die comprises a first die active area and the first side of the second die comprises a second die active area, wherein an inorganic dielectric layer is on the first die active area and is on the second die active area.
11. 11. The apparatus of claim 10, wherein the bridge structure comprises copper or copper alloys and the inorganic dielectric layer comprises at least one of silicon, oxygen, nitrogen or carbon.
12. 12. A system, comprising: a first side of a first die on a surface of a thermal solution; a first side of a second die adjacent the first die; a bridge structure on a second side of the first die and on a second side of the second die, wherein a first portion of the bridge structure is directly on a first metal feature of the second side of the first die, and a second portion of the bridge structure is directly on a second metal feature of the second side of the second die; and a package substrate, wherein the second side of the first die and the second side of the second die are coupled to the package substrate.
13. 13. The system of claim 12, wherein the bridge structure comprises a plurality of conductive traces, wherein a dielectric spacer is between the first die and the second die and wherein the bridge structure is over the dielectric spacer.
14. 14. The system of claim 13, wherein a length of an individual one of the plurality of conductive traces comprises less than about 200 microns, and wherein a pitch between a first individual one of the plurality of conductive traces and a second individual one of the plurality of conductive traces comprises less than about 2 microns.
15. 15. The system of claim 13, wherein the first metal feature comprises a first integrated circuit (IC) contact structure and the second metal features comprises a second IC contact structure, wherein a first via structure of an individual one of the plurality of conductive traces is directly on the first IC contact structure and a second via structure of the individual one of the plurality of conductive traces is directly on the second IC contact structure.
16. 16. The system of claim 15, wherein a pitch between the first integrated circuit IC contact structure and the second IC contact structure is less than about 9 microns, and wherein a power supply is coupled with the first die and the second die.
17. 17. A method, comprising: providing a thermal solution comprising a first side of a first die and a first side of a second die on a surface thereof, wherein a second side of the first die comprises a first integrated circuit (IC) contact structure and wherein a second side of the second die comprises a second IC contact structure, and wherein a dielectric spacer is between the first die and the second die; forming an inorganic dielectric layer on the second side of the first die and on the second side of the second die and on the dielectric spacer; and forming a plurality of conductive traces on the inorganic dielectric layer, wherein a first terminal end of an individual one of the plurality of conductive traces are on the first integrated circuit (IC) contact structure and a second terminal end of the individual one of the plurality of conductive traces are on the second IC contact structure.
18. 18. The method of claim 17, further comprising forming an additional plurality of conductive traces adjacent to the plurality of conductive traces on the inorganic dielectric layer.
19. 19. The method of claim 18, further comprising forming one or more conductive bumps on the additional plurality of conductive traces.
20. 20. The method of claim 19, further comprising attaching a package substrate to the one or more conductive bumps.

Description

METHODS OF FORMING WAFER LEVEL MULTI-DIE SYSTEM FABRIC INTERCONNECT STRUCTURES CLAIM OF PRIORITY [0001] This application claims priority to U.S. Patent Application No. 18/217,049, filed on June 30, 2023 and titled “METHODS OF FORMING WAFER LEVEL MULTI-DIE SYSTEM FABRIC INTERCONNECT STRUCTURES,” which is incorporated by reference in its entirety for all purposes. BACKGROUND [0002] In electronics manufacturing, integrated circuit (IC) packaging is a stage of manufacture where an IC that has been fabricated on a die or chip comprising a semiconducting material is coupled to a supporting case or “package” that can protect the IC from physical damage and support electrical interconnect suitable for further connecting to a host component, such as a printed circuit board (PCB). In the IC industry, the process of fabricating a package is often referred to as packaging, or assembly. [0003] As demand for high performance computing (HPC) continues to rise, integration of heterogeneous devices within an IC package has become an important performance driver. Some high density die-to-die interconnect schemes utilize a silicon bridge die. A bridge die can provide high wiring density by leveraging standard silicon wafer manufacturing processing, as well as providing robust mechanical and environmental protections of fine pitch wiring. Common bridge schemes include embedded multi-die interconnect bridge structures, where the silicon bridge die is embedded in the package substrate, and utilizing an interposer layer that integrates a bridge die. However, large die area consumption and wire length considerations can limit the maximum signal bandwidth achievable with such die interconnect schemes. BRIEF DESCRIPTION OF THE DRAWINGS [0004] The subject matter described herein is illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements. In the figures: [0005] FIG. 1A and FIG. 1C are cross-sectional views of IC package structures comprising die-to-die bridge structures, in accordance with some embodiments. [0006] FIG. IB is a top view of an IC package structure comprising die-to-die bridge structures, in accordance with some embodiments. [0007] FIGS. 2A-2M illustrate cross-sectional views of structures formed during the fabrication of package structures having die-to-die bridge structures, in accordance with some embodiments. [0008] FIG. 3 illustrates a flow chart of a process for the fabrication of IC package structures having die-to-die bridge structures, in accordance with some embodiments. [0009] FIG. 4 is a functional block diagram of an electronic computing device, in accordance with some embodiments of the present disclosure. DETAIEED DESCRIPTION [0010] Embodiments are described with reference to the enclosed figures. While specific configurations and arrangements are depicted and discussed in detail, it should be understood that this is done for illustrative purposes only. Persons skilled in the relevant art will recognize that other configurations and arrangements are possible without departing from the spirit and scope of the description. It will be apparent to those skilled in the relevant art that techniques and/or arrangements described herein may be employed in a variety of other systems and applications other than what is described in detail herein. [0011] Reference is made in the following detailed description to the accompanying drawings, which form a part hereof and illustrate exemplary embodiments. Further, it is to be understood that other embodiments may be utilized and structural and/or logical changes may be made without departing from the scope of claimed subject matter. It should also be noted that directions and references, for example, up, down, top, bottom, and so on, may be used merely to facilitate the description of features in the drawings. Therefore, the following detailed description is not to be taken in a limiting sense and the scope of claimed subject matter is defined solely by the appended claims and their equivalents. [0012] In the following description, numerous details are set forth. However, it will be apparent to one skilled in the art, that embodiments may be practiced without these specific details. In some instances, well-known methods and devices are shown in block diagram form, rather than in detail, to avoid obscuring the embodiments. Reference throughout this specification to “an embodiment” or “one embodiment” or “some embodiments” means that a particular feature, structure, function, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the