EP-4736233-A1 - SEMICONDUCTOR PACKAGE WITH CHIP STACK AND ORTHOGONAL INTERCONNECTION BRIDGE

Abstract

A package structure includes a substrate having an upper surface; a first chip package positioned on the upper surface of the substrate, the first chip package comprising a first chip having a first integrated circuit connected to a first redistribution layer; a second chip package positioned on the upper surface of the substrate, the second chip package comprising a second chip having a second integrated circuit connected to a second redistribution layer; an orthogonal bridge positioned between the first chip package and the second chip package and having an interconnection to the first redistribution layer and the second redistribution layer; and a heat spreader positioned in direct contact with at least one of the first chip package, the second chip package, or the orthogonal bridge. The orthogonal bridge is arranged substantially orthogonal to the upper surface of the substrate.

Inventors

• KNICKERBOCKER, JOHN
• FAROOQ, MUKTA GHATE
• MATSUMOTO, KEIJI

Assignees

• International Business Machines Corporation

Dates

Publication Date

20260506

Application Date

20240619

Claims (18)

1. 1. A package structure, comprising: a substrate having an upper surface; a first chip package positioned on the upper surface of the substrate, the first chip package comprising a first chip having a first integrated circuit connected to a first redistribution layer; a second chip package positioned on the upper surface of the substrate, the second chip package comprising a second chip having a second integrated circuit connected to a second redistribution layer; an orthogonal bridge positioned between the first chip package and the second chip package and having an interconnection to the first redistribution layer and the second redistribution layer; and a heat spreader positioned in direct contact with at least one of the first chip package, the second chip package, or the orthogonal bridge; wherein the orthogonal bridge is arranged substantially orthogonal to the upper surface of the substrate.
2. 2. The package structure of claim 1, wherein the heat spreader comprises at least one of aluminum, copper, tungsten, molybdenum, nickel, silicon, silicon carbide, silicon nitride, aluminum nitride, graphite, diamond, or combinations thereof.
3. 3. The package structure of claim 1, wherein the first chip package and the second chip package lack through-silicon vias.
4. 4. The package structure of claim 1, wherein the interconnections of the orthogonal bridge to the first redistribution layer and the second redistribution layer are solder interconnections.
5. 5. The package structure of claim 1, wherein a plurality of first chips in the first chip package are connected to each other via at least one of hybrid bonding, fusion bonding, or thermal compression bonding, and wherein a plurality of second chips in the second chip package are connected to each other via at least one of hybrid bonding, fusion bonding, or thermal compression bonding.
6. 6. The package structure of claim 5, wherein the plurality of first chips in the first chip package are separated by first bumps, and wherein the plurality of second chips in the second chip package are separated by second bumps.
7. 7. The package structure of claim 1 , wherein the orthogonal bridge comprises one or more of silicon, silicon carbide, silicon dioxide, diamond, a silicon nitride, a glass, a dielectric material, a solder material, polymer, copper, tantalum, tantalum nitride, nickel, gold, aluminum nitride, indium, or combinations thereof.
8. 8. A package structure, comprising: a first chip stack comprising one or more first chips; a first bridge interconnected to a first lateral edge of the first chip stack; and a heat spreader positioned in direct contact with at least one of the first chip stack or the bridge; wherein the first chip stack and a lower edge of the bridge are positioned on a planar surface of a substrate such that the first bridge extends orthogonal to the planar surface of the substrate.
9. 9. The package structure of claim 8, further comprising a second bridge having a lower edge positioned on the planar surface of the substrate, and the second bridge interconnected to a second lateral edge of the first chip stack.
10. 10. The package structure of claim 9, further comprising a second chip interconnected to an upper edge of the first bridge and to an upper edge of the second bridge.
11. 11. The package structure of claim 10, wherein the first bridge and the second bridge are cube memory chips.
12. 12. The package structure of claim 8, wherein the heat spreader comprises at least one of aluminum, copper, tungsten, molybdenum, nickel, silicon, silicon carbide, silicon nitride, aluminum nitride, graphite, diamond, or combinations thereof.
13. 13. The package structure of claim 8, wherein an interconnection of the first chip stack to the first bridge is a solder interconnection.
14. 14. The package structure of claim 8, wherein the first bridge transports at least one of current or voltage to the first chip stack.
15. 15. A method, comprising: assembling a plurality of chips into a stack without through-silicon vias, each chip of the plurality of chips having a redistribution layer; bonding the plurality of stacked chips together; bonding the bonding and stacked chips to a bridge at lateral edges of the chips to interconnect the redistribution layers to the bridge; bonding the bonded and stacked chips and the bridge to a substrate; and attaching a heat spreader to the bonded and stacked chips; wherein the bridge extends orthogonal to a planar surface of the substrate.
16. 16. The method of claim 15, wherein the plurality of chips are assembled into a stack without through-silicon vias.
17. 17. The method of claim 15, wherein the bonding of the plurality of stacked chips is by at least one or hybrid bonding, fusion bonding, or thermal compression bonding.
18. 18. The method of claim 15, further comprising underfilling space between the stacked chips.

Description

SEMICONDUCTOR PACKAGE WITH CHIP STACK AND ORTHOGONAL INTERCONNECTION BRIDGE BACKGROUND [0001] The exemplary embodiments described herein relate generally to semiconductor package structures and, more specifically, to semiconductor package structures employing bridge technologies to connect semiconductor chip stacks. [0002] Heterogeneous integration (HI) with regard to semiconductor devices allows for the realization of high speed and high bandwidth communication between chips (for example, CPU, GPU, and memory). The modular nature of HI allows for the use of packaging technologies to combine discrete chips, which may be of various sizes. [0003] Silicon bridge technology may be used with HI to connect various kinds of chips. For example, one type of silicon horizontal bridge technology is embedded multi-die interconnect bridging (EMIB), which provides an alternative solution to a silicon interposer and uses silicon only in areas where two dies are connected. Another type of silicon horizontal bridge technology is directed bonded heterogenous integration (DBHi), which involves the use of a silicon bridge directly bonded to and in between processor chips using copper pillars, thus allowing high-bandwidth low-latency low-power communication between the chips. Horizontal bridge technology may also be used in fan-out wafer-level packaging (FOWLP). Still other horizontal bridge technology for high-performance computing (HPC) applications may include 4-dimensional integration (4Di) bridging, which involves surface wiring to edges of memory chips and the joining of “cube memory chips” to packages. [0004] However, current silicon bridge technology lacks the capabilities to enable various kinds of HI architectures, including chip stacks. It is also incapable of eliminating through- silicon vias (TSVs) in chip stacks since a bridge operates to deliver power, ground, and signal to chips stacks, and the use of TSVs detracts from such operation. Also, thermal management of the overall chip structure is less efficient in current silicon bridge technology. BRIEF SUMMARY [0005] In one exemplary aspect, a package structure comprises: a substrate having an upper surface; a first chip package positioned on the upper surface of the substrate, the first chip package comprising a first chip having a first integrated circuit connected to a first redistribution layer; a second chip package positioned on the upper surface of the substrate, the second chip package comprising a second chip having a second integrated circuit connected to a second redistribution layer; an orthogonal bridge positioned between the first chip package and the second chip package and having an interconnection to the first redistribution layer and the second redistribution layer; and a heat spreader positioned in direct contact with at least one of the first chip package, the second chip package, or the orthogonal bridge. The orthogonal bridge is arranged substantially orthogonal to the upper surface of the substrate. [0006] The heat spreader may comprise at least one of aluminum, copper, or diamond. The first chip package and the second chip package may lack through-silicon vias. The interconnections of the orthogonal bridge to the first redistribution layer and the second redistribution layer may be solder interconnections. A plurality of first chips in the first chip package may be connected to each other via at least one of hybrid bonding, fusion bonding, or thermal compression bonding. A plurality of second chips in the second chip package may be connected to each other via at least one of hybrid bonding, fusion bonding, or thermal compression bonding. The plurality of first chips in the first chip package may be separated by first bumps. The plurality of second chips in the second chip package may be separated by second bumps. The orthogonal bridge may comprise one or more of silicon, silicon carbide, silicon dioxide, diamond, a silicon nitride, a glass, a dielectric material, a solder material, polymer, copper, tantalum, tantalum nitride, nickel, gold, aluminum nitride, indium, or combinations thereof. [0007] In another exemplary aspect, a package structure comprises: a first chip stack comprising one or more first chips; a first bridge interconnected to a first lateral edge of the first chip stack; and a heat spreader positioned in direct contact with at least one of the first chip stack or the bridge. The first chip stack and a lower edge of the bridge are positioned on a planar surface of a substrate such that the first bridge extends orthogonal to the planar surface of the substrate. [0008] The package structure may further comprise a second bridge having a lower edge positioned on the planar surface of the substrate, and the second bridge interconnected to a second lateral edge of the first chip stack. The package structure may further comprise a second chip interconnected to an upper edge of the first bridge and to an upper edge of the second br